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never stop thinking. octalliu tm octal e1/t1/j1 line interface component for long- and short-haul applications pef 22508 e, version 1.1 data sheet, rev. 1.0, june 2005 wireline communications
the information in this document is subject to change without notice. edition 2005-06-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet 3 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e trademarks abm ? , ace ? , aop ? , arcofi ? , asm ? , asp ? , digitape ? , duslic ? , epic ? , elic ? , falc ? , geminax ? , idec ? , inca ? , iom ? , ipat ? -2, isac ? , itac ? , iwe ? , iworx ? , musac ? , muslic ? , octat ? , optiport ? , potswire ? , quat ? , quadfalc ? , scout ? , sicat ? , sicofi ? , sidec ? , slicofi ? , smint ? , socrates ? , vinetic ? , 10basev ? , 10basevx ? are registered trademarks of infineon technologies ag. 10bases?, easyport?, vdslite? are trademarks of infineon technologies ag. microsoft ? is a registered trademark of microsoft corporation, linux ? of linus torvalds, visio ? of visio corporation, and framemaker ? of adobe systems incorporated. pef 22508 e, octal e1/t1/j1 line interface component for long- and short-haul applications revision history: 2005-06-02, rev. 1.0 previous version: page subjects (major changes since last revision)
data sheet 4 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 pin diagram pg-lbga-256 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 pin strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1 hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1 asynchronous micro controller interface (intel or motorola mode) . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1.1 mixed byte/word access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5.2 serial micro controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2.1 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.2.2 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.3 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5.5 master clocking unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.5.1 pll (reset and configuring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6 line coding and framer interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.7 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.7.1 receive line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7.2 receive line coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7.3 receive line termination (analog switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7.4 receive line monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.7.5 loss-of-signal detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7.6 receive equalization network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7.7 receive line attenuation indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7.8 receive clock and data recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7.9 receive jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7.9.1 receive jitter attenuation performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.7.9.2 jitter tolerance (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.7.9.3 output jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.7.10 dual receive elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.8 additional receiver functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.8.1 error monitoring and alarm handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.8.2 automatic modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.3 error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.8.4 one-second timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.9 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.9.1 transmit line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.9.2 transmit clock tclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.9.3 automatic transmit clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.9.4 transmit jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.9.5 dual transmit elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.9.6 programmable pulse shaper and line build-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.9.6.1 quadliu tm compatible programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table of contents
data sheet 5 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e 3.9.6.2 programming with txp(16:1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.9.7 transmit line monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.10 framer interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.11 test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.11.1 pseudo-random binary sequence generation and monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.11.2 in-band loop generation, detection and loop switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.11.3 remote loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.11.4 local loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.11.5 payload loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.11.6 alarm simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.12 multi function ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.1.1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1.2 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 61 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.1.1 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.1.2 jtag boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 6.1.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1.4 asynchronous microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1.4.1 intel bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.1.4.2 motorola bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 6.1.4.3 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.1.4.4 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.1.5 digital interface (framer interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 6.1.6 pulse templates - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.1.6.1 pulse template e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.1.6.2 pulse template t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 6.2 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 6.3 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.4 test configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.4.1 ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6.4.2 power supply test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.1 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.2 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.3 device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.4 device configuration in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.5 device configuration in t1/j1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.6 device configuration for digital clock interface mode (dcim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 8 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 8.1 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 8.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 8.3 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table of contents
data sheet 6 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2 typical multiple link application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3 typical multiple repeater application between line #1 and line #2. . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4 pin configuration (ball layout) pg-lbga-256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 6 sci interface application with point to point connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7 sci interface application with multipoint to multipoint connection . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8 sci message structure of octalliu tm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 9 frame structure of octalliu tm sci messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 10 principle of building addresses and rsta bytes in the sci ack message of the octalliu tm . . . 47 figure 11 read status byte (rsta) byte of the sci acknowledge (ack). . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12 spi read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 13 spi write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 15 block diagram of test access port and boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16 flexible master clock unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 17 receive system of one channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 18 recovered and receive clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 19 receiver configuration with integrated analog switch for receive impedance matching . . . . . . . 58 figure 20 receive line monitoring rlm (shown for one line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 21 redundancy application using rlm (shown for one line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 22 long haul redundancy application using the analog switch (shown for one line) . . . . . . . . . . . . 61 figure 23 principle of configuring the dco-r and dco-x corner frequencies . . . . . . . . . . . . . . . . . . . . . . 64 figure 24 jitter attenuation performance (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 25 jitter attenuation performance (t1/j1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26 jitter tolerance (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 27 jitter tolerance (t1/j1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 28 the receive elastic buffer as circularly organized memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 29 transmit system of one channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30 transmit line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 31 clocking and data in remote loop configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 32 measurement configuration for e1 transmit pulse template . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 33 measurement configuration for t1/j1 transmit pulse template . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 34 transmit line monitor configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35 framer interface (shown for one channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 36 remote loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 37 local loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 38 payload loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 39 pg-lbga-256-1 (plastic low profile ball grid array package), smd . . . . . . . . . . . . . . . . . . . . . 161 figure 40 mclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 41 jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 42 reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 43 intel non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 44 intel multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 45 intel read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 46 intel write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 47 motorola read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 48 motorola write cycle timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 49 sci interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 50 spi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 51 fclkx output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 52 fclkr output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 53 sync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 list of figures
data sheet 7 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e figure 54 fsc timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 55 e1 pulse shape at transmitter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 56 t1 pulse shape at the cross connect point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 57 input/output waveforms for ac testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 58 device configuration for power supply testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 59 protection circuitry examples (shown for one channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 60 screen shot of the ?master clock frequency calculator? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 61 screen shot of the ?external line frontend calculator? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 list of figures
data sheet 8 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e table 1 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2 overview about the pin strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 3 data bus access (16-bit intel mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 4 data bus access (16-bit motorola mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5 selectable asynchronous bus and microprocessor interface configuration . . . . . . . . . . . . . . . . . 43 table 6 read status byte (rsta) byte of the sci acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 7 definition of control bits in commands (cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 8 sci configuration register content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9 interrupt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10 tap controller instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 11 conditions for a pll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 12 line coding and framer interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 13 receiver configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 14 external component recommendations (monitoring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 15 tristate configurations for the rdo and rclk pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 16 redundancy application using rlm, switching with only one signal . . . . . . . . . . . . . . . . . . . . . . 60 table 17 redundancy application using the analog switch, switching with only one board signal . . . . . . 61 table 18 overview dco-r (dco-x) programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 19 clocking modes of dco-r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 20 output jitter (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 21 receive (transmit) elastic buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 22 summary of alarm detection and release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 23 recommended transmitter configuration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 24 recommended pulse shaper programming for t1/j1 with registers xpm(2:0) (compatible to quadliu ) 75 table 25 recommended pulse shaper programming for e1 with registers xpm(2:0) (compatible to octalliu tm ) 76 table 26 recommended pulse shaper programming for t1 with registers txp(16:1) . . . . . . . . . . . . . . . 76 table 27 recommended pulse shaper programming for e1 with registers txp(16:1) . . . . . . . . . . . . . . . 77 table 28 supported prbs polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 29 multi function port selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 30 registers address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 31 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 32 registers access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 33 imrn overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 34 interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 35 ccbn overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 36 clear channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 37 fllb constant values (case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 38 fllb constant values (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 39 llbp constant values (case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 40 llbp constant values (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 41 rpc1 constant values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 42 xpc1 constant values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 43 pcn overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 44 port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 45 clock mode register settings for e1 or t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 table 46 txp overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 47 alarm simulation states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 48 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 49 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 50 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 51 mclk timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 list of tables
data sheet 9 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e table 52 jtag boundary scan timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 53 reset timing parameter value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 54 intel bus interface timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 55 motorola bus interface timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 56 sci timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 57 spi timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 58 fclkx timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 59 fclkr timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 60 sync timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 61 fsc timing parameter values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 62 t1 pulse template at cross connect point (t1.102 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 63 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 64 package characteristic values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 65 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 66 power supply test conditions e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 67 power supply test conditions t1/j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 68 initial values after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 69 configuration parameters (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 70 line interface configuration (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 71 configuration parameters (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 72 line interface configuration (t1/j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 73 device configuration for dcim mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 list of tables
octalliu tm pef 22508 e data sheet 10 rev. 1.0, 2005-06-02 preface the octalliu tm is an 8 channel e1/t1/j1 line interface component, it is designed to fulfill all required interfacing between 8 analog e1/t1/j1 lines and 8 digital framers. the digital functions as well as the analog characteristics can be configured either via a flexible microprocessor interface, spi interface or via a sci interface. organization of this document this data sheet is organized as follows: chapter 1 , ?introduction?: gives a general description of the product and its family, lists the key features, and presents some typical applications. chapter 2 , ?pin descriptions?: lists pin locations with associated signals, categorizes signals according to function, and describe signals. chapter 3 , ?functional description?: describes the functional blocks and principle operation modes, organized into separate sections for e1 and t1/j1 operation chapter 4 , ?registers?: gives a detailed description of all implemented registers and how to use them in different applications/configurations. chapter 5 , ?package outlines?: shows the mechanical characteristics of the device packages. chapter 6 , ?electrical characteristics?: specifies maximum ratings, dc and ac characteristics. chapter 7 , ?operational description?: shows the operation modes and how they are to be initialized (separately for e1 and t1/j1). chapter 8 , ?appendix?: gives an example for over voltage protection and information about application notes and tool support. related documentation this document refers to the following international standards (in alphabetical/numerical order): ansi/eia-656 ansi t1.102 ansi t1.231 ansi t1.403 at&t pub 43802 at&t pub 54016 at&t pub 62411 esd ass. standard eos/esd-5.1-1993 etsi ets 300 011 etsi ets 300 233 etsi tbr12 etsi tbr13 fcc part68 h.100 h-mvip ieee 1149.1 tr-tsy-000009 tr-tsy-000253 tr-tsy-000499 itu-t g.703 itu-t g.736 itu-t g.737 itu-t g.738 itu-t g.739 itu.t g.733 itu-t g.775 itu-t g.823 itu-t g.824 itu-t i.431 jt-g703 jt-g704 jt-g706 jt-g33 jt-i431 mil-std. 883d ul 1459
data sheet 11 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e introduction 1 introduction the octalliu tm is the latest addition to infineon?s family of sophisticated e1/t1/j1 line interface components. this monolithic 8 channel device is designed to fulfill all required interfacing between eight analog e1/t1/j1 lines and eight digital framer interfaces for world market telecommunication systems. the device is supplied in a 17 mm x 17 mm lbga package, and is designed to minimize the number of external components required, so reducing system costs and board space. due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the according international standards. crystal-less jitter attenuation with only one master clock source reduces the amount of required external components. equipped with a flexible microprocessor interface, a sci and a spi interface, it connects to various control processor environment. a standard boundary scan interface is provided to support board level testing. lbga device packaging, minimum number of external components and low power consumption lead to reduced overall system costs. other members of the falc ? family are the quadliu tm supporting four line interface components on a single chip, the octalfalc tm and the quadfalc ? e1/t1/j1 framer and line interface components for long-haul and short- haul applications, supporting 8 or 4 channels on a single chip respectively.
version 1.1 type package pef 22508 e pg-lbga-256-1 p-lbga-256-1 data sheet 12 rev. 1.0, 2005-06-02 octal e1/t1/j1 line inte rface component for long- and short-haul applications octalliu tm pef 22508 e 1.1 features line interface high-density, generic interface for all e1/t1/j1 applications eight analog receive and transmit circuits for long-haul and short-haul applications e1 or t1/j1 mode selectable data and clock recovery using an integrated digital phase-locked loop clock generator for jitter-free transmit clocks per channel jitter specifications of itu-t i.431, g.703, g.736 (e1), g.823 (e1) and at&t tr62411 (t1/j1) and pub 62411 are met maximum line attenuation up to -43 db at 1024 khz (e1) and up to - 36 db at 772 khz (t1/j1) flexible programmable transmit pulse shapes for e1 and t1/j1 pulse masks programmable line build-out for csu signals according to ansi t1. 403 and fcc68: 0 db, -7.5 db, -15 db, -22.5 db (t1/j1) programmable low transmitter output impedances for high transmit return loss and generic e1/t1/j1 applications tristate function of the analog transmit line outputs transmit line monitor protecting the device from damage flexible tristate functions of the digital receive outputs receive line monitor mode integrated analog switch for generic e1/t1/j1 applications to meet termination resistance 75/120 ? for e1, 100 ? for t1 and 110 ? for j1 crystal-less wander and jitter attenuation/compensation according to tr 62411, ets-tbr 12/13, pub 62411 common master clock reference for e1 and t1/j1 with any frequency within 1.02 and 20 mhz power-down function support of automatic protection switching dual-rail or single-rail digital inputs and outputs unipolar cmi for interfacing fiber-optical transmission routes selectable line codes (e1: hdb3, ami/t1: b8zs, ami with zcs) loss-of-signal indication with programmable thresholds according to itu-t g.775, ets300233 (e1) and ansi t1.403 (t1/j1) optional data stream muting upon los detection programmable receive slicer threshold local loop, digital loop and remote loop for diagnostic purposes. automatic remote loop switching is possible with in-band and out-band loop codes low power device, two power supply voltages: 1.8 v and 3.3 v
data sheet 13 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e introduction alarm and performance monitoring per second 16-bit counter for code violations, prbs bit errors insertion and extraction of alarm indication signals (ais) single-bit defect insertion flexible clock frequency for receiver and transmitter dual elastic stores for both, receive and transmit route clock wander and jitter compensation; controlled slip capability and slip indication programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass programmable in-band loop code detection and generation (tr62411) local loop back, payload loop back land remote loop back capabilities (tr54016) flexible pseudo-random binary sequence generator and monitor microprocessor interfaces asynchronous 8/16-bit microprocessor bus interface (intel or motorola type selectable) spi bus interface sci bus interface all registers directly accessible multiplexed and non-multiplexed address bus operations on asynchronous 8/16-bit microprocessor bus interface hard/software reset options extended interrupt capabilities one-second timer (internal or external timing reference) general boundary scan standard ieee 1149.1 pg-lbga-256-1 package; body size 17 mm 17 mm; ball pitch 1.0 mm temperature range from -40 to +85 c 1.8 v and 3.3 v power supply typical power consumption 140 mw per channel applications wireless base stations e1/t1/j1 atm gateways, multiplexer e1/t1/j1 c hannel & d ata s ervice u nits (csu, dsu) e1/t1/j1 internet access equipment lan/wan router isdn pri, pabx d igital a ccess c rossconnect s ystems (dacs) sonet/sdh add/drop multiplexer
octalliu tm pef 22508 e introduction data sheet 14 rev. 1.0, 2005-06-02 1.2 logic symbol figure 1 logic symbol octalliu tm pef 22508 e v1.1 p-lbga256 octalliu_logic_symbol vddr(1:8) rl1(8:1) rl2(8:1) xl1(8:1) xl2(8:1) tdi tms tck trs tdo rdo(8:1) rpa(8:1) rpb(8:1) rpc(8:1) xdi(8:1) xpa(8:1) xpb(8:1) vddx(1:8) d(15:0)/sci a(10:0) cs wr/rw rd/ds bhe/ble ale dbw im(1:0) res int mclk sync fsc microprocessor interface transmi t digital interfac e receive digital interfac e transmit line interface receive line interface boundary scan interface vddc vss xl3(8:1) xl4(8:1) ready/tdack mode (sci- or spi-bus) rls(8:1) vdd fclkr(8:1) fclkx(8:1)
data sheet 15 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e introduction 1.3 typical applications figure 2 shows a multiple link application, figure 3 a repeater application using the octalliu tm . figure 2 typical multiple link application figure 3 typical multiple repeater application between line #1 and line #2 o ct alli u_f0195 octal liu tm peb 22508 fr amer asic microprocessor system highway 8 x e1/t1/j1 receive & transmit . . . o ct alli u_f0069 1/4 octalliu tm rl1.1 rl2.1 rdo1 rdon1 xl1.1 xl2.1 xdi1 xdin1 bidirectional line #1 rl1.2 rl2.2 xl1.2 xl2.2 bidirectional line #2 rdo2 rdon2 xdi2 xdin2 fclkr2 fclkx1 fclkx2 fclkr1
octalliu tm pef 22508 e pin descriptions data sheet 16 rev. 1.0, 2005-06-02 2 pin descriptions in this chapter the function and placement of all pins are described. 2.1 pin diagram pg-lbga-256 (top view) figure 4 shows the ball layout of the octalliu tm . figure 4 pin configuration (ball layout) pg-lbga-256 a bcdefg h jkl m n 16 reserved xpb8 xpa8 fclkx8 fclkr8 rpa7 a0 rd a3 a9 fclkx6 fclkr6 rpc5 15 rl27 vss xdip8 rpb8 xpb7 rdop7 ale wr a4 a8 rpc6 xpb5 rpb5 14 rls7 vss xl37 xl17 xpa7 rpb7 ready reserved a2 a7 xdip6 xpa5 xl16 13 rl17 vddr7 xl47 xl27 rdop8 fclkr7 sync bhe a1 a6 rpb6 rpa6 xl26 12 vss vss vddx7 vddx7 rpa8 fclkx7 sec cs a5 a10 xpa6 fclkx5 vddx6 11 rl18 vddr8 vss xl38 xl18 rpc8 vddc i nt vddp vddp xpb6 xdi p5 xl15 10 rl28 rls8 vss xl48 xl28 rpc7 vss vss vss vss vddc rdop6 xl25 9 vss vss vddx8 vddx8 rpc2 xdip7 vss vss vss vss vddc tdi vddx5 8 rl21 vss vddx1 vddx1 rpb2 fclkx2 vss vss vss vss vddc tms vddx4 7 rls1 vddr1 xl31 xl11 rpc1 xdip2 vss vss vss vss xpa3 xl14 xl34 6 rl11 im1 xl41 xl21 rpa2 xpb2 vss vddpll mclk vss rdop3 xl24 xl44 5 vss vddr2 vddx2 vddx2 xdi p1 xpa2 vddp vddp vddp vddp xdip3 rpb4 vddx3 4 rl12 im0 xl32 xl12 rdop2 d12 vddc vddc vddc fclkr3 rpa3 rpa4 xl13 3 rls2 res xl42 xl22 xpa1 d13 d9 d5 d3 d2 fclkx3 rdopp4 xl23 2 rl22 vss rdop1 rpb1 xpb1 d14 d10 d7 d4 d0 rpb3 xpb3 rpc4 1 reserved rpa1 fclkr1 fclkx1 fclkr2 d15 d11 d8 d6 d1 rpc3 fclkr4 fclkx4 prt fclkr5 rpa5 reserved rdop5 vss rl26 xl36 vss rls6 xl46 vss rl16 vddx6 vddr6 vss xl35 vddr5 rl15 xl45 tdo rls5 vddx5 tck rl25 vddx4 vss vss vss rls4 rl24 trsq vddr4 rl14 vddx3 dbw vss xl33 vddr3 rl13 xl43 vss rls3 xdi p4 vss rl23 xpa4 xpb4 reserved
data sheet 17 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions 2.2 pin definitions and functions the following table describes all pins and their functions: table 1 i/o signals pin no. ball no. name pin type buffer type function operation mode selection and device initialization b3 res i pu hardware reset active low b6 im1 i pu interface mode selection 00 b : asynchronous intel bus mode. 01 b : asynchronous motorola bus mode 10 b : spi bus slave mode. 11 b : sci bus slave mode b4 im0 i pu asynchronous and serial micro controller interfaces k12 a10 i pu address bus line 10 (msb) k16 a9 i pu address bus line 9 k15 a8 i pu address bus line 8 k14 a7 i pu address bus line 7 k13 a6 i pu address bus line 6 j12 a5 i pu address bus line 5 a5 i pu sci source address bit 5 (msb) only used if sci interface mode is selected by im(1:0) = 11b. j15 a4 i pu address bus line 4 a4 i pu sci source address bit 4 only used if sci interface mode is selected by im(1:0) = 11b. j16 a3 i pu address bus line 3 a3 i pu sci source address bit 3 only used if sci interface mode is selected by im(1:0) = 11b. j14 a2 i pu address bus line 2 a2 i pu sci source address bit 2 only used if sci interface mode is selected by im(1:0) = 11b. j13 a1 i pu address bus line 1 a1 i pu sci source address bit 1 only used if sci interface mode is selected by im(1:0) = 11b. g16 a0 i pu address bus line 0 a0 i pu sci source address bit 0 (lsb) only used if sci interface mode is selected by im(1:0) = 11b.
octalliu tm pef 22508 e pin descriptions data sheet 18 rev. 1.0, 2005-06-02 1f d15 io pu data bus line 15 pll10 i pu pll programming bit 10 only used if sci or spi interface mode is selected by im(1:0) = 1xb. 2f d14 io pu data bus line 14 pll9 i pu pll programming bit 9 only used if sci or spi interface mode is selected by im(1:0) = 1xb. f3 d13 io pu data bus line 13 pll8 i pu pll programming bit 8 only used if sci or spi interface mode is selected by im(1:0) = 1xb. f4 d12 io pu data bus line 12 pll7 i pu pll programming bit 7 only used if sci or spi interface mode is selected by im(1:0) = 1xb. g1 d11 io pu data bus line 11 pll6 i pu pll programming bit 6 only used if sci or spi interface mode is selected by im(1:0) = 1xb. g2 d10 io pu data bus line 10 pll5 i pu pll programming bit 5 only used if sci or spi interface mode is selected by im(1:0) = 1xb. g3 d9 io pu data bus line 9 pll4 i pu pll programming bit 4 only used if sci or spi interface mode is selected by im(1:0) = 1xb. h1 d8 io pu data bus line 8 pll3 i pu pll programming bit 3 only used if sci or spi interface mode is selected by im(1:0) = 1xb. h2 d7 io pu data bus line 7 pll2 i pu pll programming bit 2 only used if sci or spi interface mode is selected by im(1:0) = 1xb. j1 d6 io pu data bus line 6 pll1 i pu pll programming bit 1 only used if sci or spi interface mode is selected by im(1:0) = 1xb. h3 d5 io pu data bus line 5 pll0 i pu pll programming bit 0 only used if sci or spi interface mode is selected by im(1:0) = 1xb. j2 d4 io pu data bus line 4 table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 19 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions j3 d3 io pu data bus line 3 k3 d2 io pu data bus line 2 sci_clk i ? sci bus clock only used if sci interface mode is selected by im(1:0) = 11b. sclk i ? spi bus clock only used if spi interface mode is selected by im(1:0) = 10b. k1 d1 io pu data bus line 1 sci_rxd i pu sci bus serial data in only used if sci interface mode is selected by im(1:0) = 11b. sdi i pu spi serial data in only used if spi interface mode is selected by im(1:0) = 10b. k2 d0 io pu data bus line 0 sci_txd i pp or od sci bus serial data out only used if sci interface mode is selected by im(1:0) = 11b. sdo i pu spi bus serial data out only used if spi interface mode is selected by im(1:0) = 10b. g15 ale i pu address latch enable a high on this line indicates an address on an external multiplexed address/data bus. the address information provided on lines a(10:0) is internally latched with the falling edge of ale. this function allows the octalliu tm to be connected to a multiplexed address/data bus without the need for external latches. in this case, pins a(7:0) must be connected to the data bus pins externally. in case of demultiplexed mode this pin can be connected directly to vdd or can be left open. h16 rd i pu read enable intel bus mode. this signal indicates a read operation. when the octalliu tm is selected via cs, the rd signal enables the bus drivers to output data from an internal register addressed by a(10:0) to the data bus. ds i pu data strobe motorola bus mode. this pin serves as input to control read/write operations. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 20 rev. 1.0, 2005-06-02 h15 wr i pu write enable intel bus mode. this signal indicates a write operation. when cs is active the octalliu tm loads an internal register with data provided on the data bus. rw i pu read/write select motorola bus mode. this signal distinguishes between read and write operation. r5 dbw i pu data bus width select bus interface mode a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe / ble . h13 bhe i pu bus high enable intel bus mode. if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus d(15:8). in 8-bit bus interface mode this signal has no function and should be tied to vdd or left open. ble i pu bus low enable motorola bus mode. if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus d(7:0). in 8-bit bus interface mode this signal has no function and should be tied to vdd or left open. h12 cs i pu chip select low active chip select. h11 int o ? interrupt request interrupt request. int serves as general interrupt request for all interrupt sources. these interrupt sources can be masked via registers imr(7:0). interrupt status is reported via registers gis (global interrupt status) and isr(7:0). output characteristics (push-pull active low/high, open drain) are determined by programming register ipc. g14 ready o ? data ready only if intel bus mode is selected. asynchronous handshake signal to indicate successful read or write cycle. dtack o ? data acknowledge only if motorola bus mode is selected. asynchronous handshake signal to indicate successful read or write cycle. line interface receiver table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 21 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions a6 rl1.1 i (analog) ? line receiver input 1, port 1 analog input from the external transformer. selected if lim1.drs is cleared. roid1 i ? receive optical interface data, port 1 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. a8 rl2.1 i (analog) ? line receiver input 2, port 1 analog input from the external transformer. selected if lim1.drs is cleared. a7 rls21 io (analog) ? receive line switch, port 1 connector of the analog switch. a4 rl1.2 i (analog) ? line receiver input 1, port 2 analog input from the external transformer. selected if lim1.drs is cleared. roid2 i ? receive optical interface data, port 2 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. a2 rl2.2 i (analog) ? line receiver input 2, port 2 analog input from the external transformer. selected if lim1.drs is cleared. a3 rls22 io (analog) ? receive line switch, port 2 connector of the analog switch. t4 rl1.3 i (analog) ? line receiver input 1, port 3 analog input from the external transformer. selected if lim1.drs is cleared. roid3 i ? receive optical interface data, port 3 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. t2 rl2.3 i (analog) ? line receiver input 2, port 3 analog input from the external transformer. selected if lim1.drs is cleared. t3 rls23 io (analog) ? receive line switch, port 3 connector of the analog switch. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 22 rev. 1.0, 2005-06-02 t6 rl1.4 i (analog) ? line receiver input 1, port 4 analog input from the external transformer. selected if lim1.drs is cleared. roid4 i ? receive optical interface data, port 4 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. t7 rl2.4 i (analog) ? line receiver input 2, port 4 analog input from the external transformer. selected if lim1.drs is cleared. r7 rls24 io (analog) ? receive line switch, port 4 connector of the analog switch. t11 rl1.5 i (analog) ? line receiver input 1, port 5 analog input from the external transformer. selected if lim1.drs is cleared. roid5 i ? receive optical interface data, port 5 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. t9 rl2.5 i (analog) ? line receiver input 2, port 5 analog input from the external transformer. selected if lim1.drs is cleared. t10 rls25 io (analog) ? receive line switch, port 5 connector of the analog switch. t13 rl1.6 i (analog) ? line receiver input 1, port 6 analog input from the external transformer. selected if lim1.drs is cleared. roid6 i ? receive optical interface data, port 6 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. t15 rl2.6 i (analog) ? line receiver input 2, port 6 analog input from the external transformer. selected if lim1.drs is cleared. t14 rls26 io (analog) ? receive line switch, port 6 connector of the analog switch. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 23 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions a13 rl1.7 i (analog) ? line receiver input 1, port 7 analog input from the external transformer. selected if lim1.drs is cleared. roid7 i ? receive optical interface data, port 7 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. a15 rl2.7 i (analog) ? line receiver input 2, port 7 analog input from the external transformer. selected if lim1.drs is cleared. a14 rls27 io (analog) ? receive line switch, port 7 connector of the analog switch. a11 rl1.8 i (analog) ? line receiver input 1, port 8 analog input from the external transformer. selected if lim1.drs is cleared. roid8 i ? receive optical interface data, port 8 unipolar data received from a fiber-optical interface with 2048 kbit/s (e1) or 1544 kbit/s (t1/j1). if cmi coding is selected (mr0.rc(1:0) = 01 b and lim0.drs = 1), an internal dpll recovers clock an data; no clock signal on rclki2 is required. a10 rl2.8 i (analog) ? line receiver input 2, port 8 analog input from the external transformer. selected if lim1.drs is cleared. b10 rls28 io (analog) ? receive line switch, port 8 connector of the analog switch. line interface transmitter d7 xl1.1 o (analog) ? transmit line 1, port 1 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid1 o ? transmit optical interface data, port 1 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk2 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. d6 xl2.1 o (analog) ? transmit line 2, port 1 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 24 rev. 1.0, 2005-06-02 c7 xl3.1 i (analog) ? transmit line 3, port 1 analog transmit input 1. c6 xl4.1 i (analog) ? transmit line 4, port 1 analog transmit input 2. d4 xl1.2 o (analog) ? transmit line 1, port 2 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid2 o ? transmit optical interface data, port 2 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk2 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. d3 xl2.2 o (analog) ? transmit line 2, port 2 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. c4 xl3.2 i (analog) ? transmit line 3, port 2 analog transmit input 1. c3 xl4.2 i (analog) ? transmit line 4, port 2 analog transmit input 2. n4 xl1.3 o (analog) ? transmit line 1, port 3 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid3 o ? transmit optical interface data, port 3 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk3 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 25 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions n3 xl2.3 o (analog) ? transmit line 2, port 3 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xfm3 o ? transmit frame marker, port 3 this digital output marks the first bit of every frame transmitted on port xdop. this function is only available in the optical interface mode (lim1.drs = 1 and mr0.xc1 = 0). data is clocked on positive transitions of xclk3. after reset this pin is in high- impedance state until register lim1.drs is set and xpm2.xlt cleared. in remote loop configuration the xfm3 marker is not valid. p4 xl3.3 i (analog) ? transmit line 3, port 3 analog transmit input 1. p3 xl4.3 i (analog) ? transmit line 4, port 3 analog transmit input 2. m7 xl1.4 o (analog) ? transmit line 1, port 4 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid4 o ? transmit optical interface data, port 4 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk4 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. m6 xl2.4 o (analog) ? transmit line 2, port 4 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. n7 xl3.4 i (analog) ? transmit line 3, port 4 analog transmit input 1. n6 xl4.4 i (analog) ? transmit line 4, port 4 analog transmit input 2. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 26 rev. 1.0, 2005-06-02 n11 xl1.5 o (analog) ? transmit line 1, port 5 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid5 o ? transmit optical interface data, port 5 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk5 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. n10 xl2.5 o (analog) ? transmit line 2, port 5 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. p11 xl3.5 i (analog) ? transmit line 3, port 5 analog transmit input 1. p10 xl4.5 i (analog) ? transmit line 4, port 5 analog transmit input 2. n14 xl1.6 o (analog) ? transmit line 1, port 6 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid6 o ? transmit optical interface data, port 6 . data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk6 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. n13 xl2.6 o (analog) ? transmit line 2, port 6 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. p14 xl3.6 i (analog) ? transmit line 3, port 6 analog transmit input 1. p13 xl4.6 i (analog) ? transmit line 4, port 6 analog transmit input 2. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 27 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions d14 xl1.7 o (analog) ? transmit line 1, port 7 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid7 o ? transmit optical interface data, port 7 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk7 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. d13 xl2.7 o (analog) ? transmit line 2, port 7 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. c14 xl3.7 i (analog) ? transmit line 3, port 7 analog transmit input 1. c13 xl4.7 i (analog) ? transmit line 4, port 7 analog transmit input 2. e11 xl1.8 o (analog) ? transmit line 1, port 8 analog output to the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. xoid8 o ? transmit optical interface data, port 8 data in cmi code is shifted out with 50% or 100% duty cycle on both transitions of xclk8 according to the cmi coding. output polarity is selected by bit lim0.xdos (after reset: data is sent active high). the single-rail mode is selected if lim1.drs is set and mr0.xc1 is cleared. after reset this pin is in high-impedance state until register lim1.drs is set and xpm2.xlt is cleared. e10 xl2.8 o (analog) ? transmit line 2, port 8 analog output for the external transformer. selected if lim1.drs is cleared. after reset this pin is in high- impedance state until bit mr0.xc1 is set and xpm2.xlt is cleared. d11 xl3.8 i (analog) ? transmit line 3, port 8 analog transmit input 1. d10 xl4.8 i (analog) ? transmit line 4, port 8 analog transmit input 2. clock signals table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 28 rev. 1.0, 2005-06-02 j6 mclk i ? master clock a reference clock of better than 32 ppm accuracy in the range of 1.02 to 20 mhz must be provided on this pin. the octalliu tm internally derives all necessary clocks from this master (see registers gcm(6:1)). g13 sync i pu clock synchronization of dco-r if a clock is detected on pin sync the dco-r circuitry of the octalliu tm synchronizes to this 1.544/2.048 mhz clock (see lim0.mas, cmr1.dcs and cmr2.dcf). additionally, in master mode the octalliu tm is able to synchronize to an 8 khz reference clock (ipc.ssyf = 1). if not connected, an internal pull-up transistor ensures high input level. g12 fsc o ? 8 khz frame synchronization the optionally synchronization pulse is active high or low for one 2.048/1.544 mhz cycle (pulse width = 488 ns for e1and 648 ns or t1/j1). digital (framer) interface receive c2 rdo1 o ? receive data out, port 1 received data at rl1, rl2 is sent to rdop, rdon. clocking of data is done with the rising or falling edge of rclk. c1 fclkr1 i/o pu framer data clock receive, port 1 input if pc5.csrp = 0, output if pc5.csrp = 1. e4 rdo2 o ? receive data out, port 2 see description of rdop1. e1 fclkr2 i/o pu framer data clock receive, port 2 see description of fclkr1. l6 rdo3 o ? receive data out, port 3 see description of rdop1. k4 fclkr3 i/o pu framer data clock receive, port 3 see description of fclkr1. m3 rdo4 o ? receive data out, port 4 see description of rdop1. m1 fclkr4 i/o pu framer data clock receive, port 4 see description of fclkr1. p15 rdo5 o ? receive data out, port 5 see description of rdop1. p16 fclkr5 i/o pu framer data clock receive, port 5 see description of fclkr1. m10 rdo6 o ? receive data out, port 6 see description of rdop1. m16 fclkr6 i/o pu framer data clock receive, port 6 see description of fclkr1. f15 rdo7 o ? receive data out, port 7 see description of rdop1. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 29 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions f13 fclkr7 i/o pu framer data clock receive, port 7 see description of fclkr1. e13 rdo8 o ? receive data out, port 8 see description of rdop1. e16 fclkr8 i/o pu framer data clock receive, port 8 see description of fclkr1. digital (framer) interface transmit e5 xdi1 i ? transmit data in, port 1 nrz transmit data received from the framer. latching of data is done with rising or falling transitions of fclkx1 according to bit dic3.resx. d1 fclkx1 i/o ? framer data clock transmit, port 1 f7 xdi2 i ? transmit data in, port 2 see description of xdi1. f8 fclkx2 i/o ? framer data clock transmit, port 2 see description of fclkx1. l5 xdi3 i ? transmit data in, port 3 see description of xdi1. l3 fclkx3 i/o ? framer data clock transmit, port 3 see description of fclkx1. p2 xdi4 i ? transmit data in, port 4 see description of xdi1. n1 fclkx4 i/o ? framer data clock transmit, port 4 see description of fclkx1. m11 xdi5 i ? transmit data in, port 5 see description of xdi1. m12 fclkx5 i/o ? framer data clock transmit, port 5 see description of fclkx1. l14 xdi6 i ? transmit data in, port 6 see description of xdi1. l16 fclkx6 i/o ? framer data clock transmit, port 6 see description of fclkx1. f9 xdi7 i ? transmit data in, port 7 see description of xdi1. f12 fclkx7 i/o ? framer data clock transmit, port 7 see description of fclkx1. c15 xdi8 i ? transmit data in, port 8 see description of xdi1. d16 fclkx8 i/o ? framer data clock transmit, port 8 see description of fclkx1. multi function pins table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 30 rev. 1.0, 2005-06-02 b1 rpa1 i/o pu/? receive multifunction pins a to c, port 1 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions are described below. d2 rpb1 i/o pu/? e7 rpc1 i/o pu/? b1 rpa1 i pu receive line termination (rlt), port 1 pc(1:3).rpc(3:0) = 1000 b . these input function controls together with lim0.rtrs the analog switch of the receive line interface: a logical equivalence is build out of lim0.rtrs and rlt. d2 rpb1 i pu e7 rpc1 i pu b1 rpa1 i pu general purpose input (gpi), port 1 pc(1:3).rpc(3:0) = 1001 b . the pin is set to input. the state of this input is reflected in the register bits mfpi.rpa, mfpi.rpb or mfpi.rpc respectively. d2 rpb1 e7 rpc1 b1 rpa1 o ? general purpose output high (gpoh), port 1 pc(1:3).rpc(3:0) = 1010 b . the pin level is set fix to high level. d2 rpb1 e7 rpc1 b1 rpa1 o ? general purpose output low (gpol), port 1 pc(1:3).rpc(3:0) = 1011 b . the pin level is set fix to low level. d2 rpb1 e7 rpc1 b1 rpa1 o ? loss of signal indication output (los), port 1 pc(1:3).rpc(3:0) = 1100 b . the output reflects the loss of signal status as readable in lsr0.los. d2 rpb1 e7 rpc1 b1 rpa1 o ? receive data output negative (rdon), port 1 pc(1:3).rpc(3:0) = 1110 b . receive data output negative for dual rail mode on digital (framer) interface (lim3.drr = 1). bipolar violation output for single rail mode on digital (framer) interface (lim3.drr = 0). d2 rpb1 e7 rpc1 b1 rpa1 o ? receive clock output (rclk), port 1 pc(1:3).rpc(3:0) = 1111 b . default setting after reset receive clock output rclk. after reset rclk is configured to be internally pulled up weekly. by setting of pc5.crp rclk is an active output. rclk source and frequency selection is made by cmr1.rs(1:0) if comp = 1 or by cmr4.rs(2:0) if comp = 0. d2 rpb1 e7 rpc1 table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 31 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions e6 rpa2 i/o pu/? receive multifunction pins a to c, port 2 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. e8 rpb2 e9 rpc2 l4 rpa3 i/o pu/? receive multifunction pins a to c, port 3 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. l2 rpb3 l1 rpc3 m4 rpa4 i/o pu/? receive multifunction pins a to c, port 4 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. m5 rpb4 n2 rpc4 table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 32 rev. 1.0, 2005-06-02 r16 rpa5 i/o pu/? receive multifunction pins a to c, port 5 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. n15 rpb5 n16 rpc5 m13 rpa6 i/o pu/? receive multifunction pins a to c, port 6 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. l13 rpb6 l15 rpc6 f16 rpa7 i/o pu/? receive multifunction pins a to c, port 7 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. f14 rpb7 f10 rpc7 table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 33 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions e12 rpa8 i/o pu/? receive multifunction pins a to c, port 8 depending on programming of bits pc(1:3).rpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset these ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resr latching/transmission of data is done with the rising or falling edge of fclkr. if not connected, an internal pull- up transistor ensures a high input level. an input function must not be selected twice or more. selectable pin functions as described for port 1. d15 rpb8 f11 rpc8 e3 xpa1 i/o pu/? transmit multifunction pins a and b, port 1 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions are described below. e2 xpb1 i/o pu/? e3 xpa1 i pu transmit clock (tclk), port 1 pc(1:2).xpc(3:0) = 0011 b a 2.048/8.192 mhz (e1) or 1.544/6.176 mhz (t1/j1) clock has to be sourced by the framer if the internally generated transmit clock (generated by dco-x) shall not be used. optionally this input is used as a synchronization clock for the dco-x circuitry with a frequency of 2.048 (e1) or 1.544 mhz (t1/j1). e2 xpb1 i pu e3 xpa1 o ? transmit clock (xclk), port 1 pc(1:2).xpc(3:0) = 0111 b transmit line clock of 2.048 mhz (e1) or 1.544 mhz (t1/j1) derived from fclkx/r, rclk or generated internally by dco circuitries. e2 xpb1 o ? e3 xpa1 i pu transmit line tristate (xlt), port 1 pc(1:2).xpc(3:0) = 1000 b a high level on this port sets the transmit lines xl1/2 or xdop/n into tristate mode. this pin function is logically ord with register bit xpm2.xlt. e2 xpb1 i pu table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 34 rev. 1.0, 2005-06-02 e3 xpa1 i pu general purpose input (gpi), port 1 pc(1:2).xpc(3:0) = 1001 b . the pin is set to input. the state of this input is reflected in the register bits mfpi.xpa, mfpi.xpb or mfpi.xpc respectively. e2 xpb1 i pu e3 xpa1 o ? general purpose output high (gpoh), port 1 pc(1:2).xpc(3:0) = 1010 b . the pin level is set fix to high level. e2 xpb1 o ? e3 xpa1 o ? general purpose output low (gpol), port 1 pc(1:2).xpc(3:0) = 1011 b . the pin level is set fix to high level. e2 xpb1 o ? e3 xpa1 i pu transmit data input negative (xdin), port 1 pc(1:2).xpc(3:0) = 1101 b . transmit data input negative for dual rail mode on framer side (lim3.drx = 1). depending on bit dic3.resx latching of data is done with the rising or falling edge of fclkx. e2 xpb1 i pu e3 xpa1 i pu transmit line tristate, low active, port 1 xlt : pc(1:2).xpc(3:0) = 1110 b . a low level on this port sets the transmit lines xl1/2 or xdop/n into tristate mode. this pin function is logically ord with register bit xpm2.xlt. e2 xpb1 i pu f5 f6 xpa2 xpb2 i/o pu/? transmit multifunction pins a and b, port 2 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. l7 m2 xpa3 xpb3 i/o pu/? transmit multifunction pins a and b, port 3 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 35 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions p1 r1 xpa4 xpb4 i/o pu/? transmit multifunction pins a and b, port 4 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. m14 m15 xpa5 xpb5 i/o pu/? transmit multifunction pins a and b, port 5 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. l12 l11 xpa6 xpb6 i/o pu/? transmit multifunction pins a and b, port 6 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 36 rev. 1.0, 2005-06-02 e14 e15 xpa7 xpb7 i/o pu/? transmit multifunction pins a and b, port 7 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. 4 4 c16 b16 xpa8 xpb8 i/o pu/? transmit multifunction pins a and b, port 8 depending on programming of bits pc(1:2).xpc(3:0) these multifunction ports carry information to the framer interface or from the framer to the octalliu tm . after reset the ports are configured to be inputs. with the selection of the appropriate pin function, the corresponding input/output configuration is achieved automatically. depending on bit dic3.resx latching/transmission of data is done with the rising or falling edge of fclkx. if not connected, an internal pull- up transistor ensures a high input level. each input function (tclk, xdin, xlt or xlt ) may only be selected once. selectable pin functions as described for port 1. power supply 7b v ddr1 s ? positive power supply for the analog receiver 1 (3.3 v) 5b v ddr2 s ? positive power supply for the analog receiver 2 (3.3 v) 4r v ddr3 s ? positive power supply for the analog receiver 3 (3.3 v) 6r v ddr4 s ? positive power supply for the analog receiver 4 (3.3 v) 11r v ddr5 s ? positive power supply for the analog receiver 5 (3.3 v) 12r v ddr6 s ? positive power supply for the analog receiver 6 (3.3 v) 13b v ddr7 s ? positive power supply for the analog receiver 7 (3.3 v) 11b v ddr8 s ? positive power supply for the analog receiver 8 (3.3 v) 8c v ddx1 s ? positive power supply for the analog transmitter 1 8d table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 37 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions 5c v ddx2 s ? positive power supply for the analog transmitter 2 5d 5n v ddx3 s ? positive power supply for the analog transmitter 3 5p 8n v ddx4 s ? positive power supply for the analog transmitter 4 8p 9n v ddx5 s ? positive power supply for the analog transmitter 5 9p 12n v ddx6 s ? positive power supply for the analog transmitter 6 12p 12c v ddx7 s ? positive power supply for the analog transmitter 7 12d 9c v ddx8 s ? positive power supply for the analog transmitter 8 9d 4g v ddc s ? positive power supply for the digital core (1.8 v) 11g 4h 4j 8l 9l 10l 6h v ddpll s ? positive power supply for the analog pll 5g v ddp s ? positive power supply for the digital pads(3.3 v) for correct operation, all v dd pins have to be connected to positive power supply. 5h 5j 5k 11j 11k table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 38 rev. 1.0, 2005-06-02 5a v ss s ? power ground common for all sub circuits (0 v) for correct operation, all v ss pins have to be connected to ground. 9a 12a 2b 8b 9b 12b 14b 15b 10c 11c 6g 7g 8g 9g 10g 7h 8h 9h 10h 7j 8j 9j 10j 6k 7k 8k 9k 10k 7p 2r 3r 8r 13r 14r 15r 5t 8t 12t boundary scan/joint test access group (jtag) table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
data sheet 39 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e pin descriptions note: od = open drain output pu = input or input/output comprising an internal pull-up device to override the internal pull-up by an external pull-down, a resistor value of 22 k ? is recommended. the pull-up devices are activated during reset, this means their state is undefined until the reset signal has been applied. unused pins containing pull-ups can be left open. p6 trs i pd test reset for boundary scan (active low). if not connected, an internal pull-up transistor ensures high input level. if the jtag boundary scan is not used, this pin must be connected to res or v ss . m9 tdi pu test data input for boundary scan. if not connected an internal pull-up transistor ensures high input level. m8 tms test mode select for boundary scan. if not connected an internal pull-up transistor ensures high input level. r9 tck test clock for boundary scan. if not connected an internal pull-up transistor ensures high input level. r10 tdo o ? test data output for boundary scan table 1 i/o signals (cont?d) pin no. ball no. name pin type buffer type function
octalliu tm pef 22508 e pin descriptions data sheet 40 rev. 1.0, 2005-06-02 2.3 pin strapping some pins are used for selection of functional modes of the octalliu tm : table 2 overview about the pin strapping pin pin strapping is used pin strapping function im(1:0) always defines the used micro controller interface a(5:0) only in sci interface mode defines the six lisps of the sci source address, see chapter 3.5.2.1 d(15:5) only in sci or spi interface mode programs the parameters n and m of the pll in the master clocking unit instead of registers gcm5 and gcm6, see chapter 3.5.5 : - d(15:11) values programs pll dividing factor m - d(10:5) values programs pll dividing factor n programming by pin strapping is equivalent to programming by register bits gcm5.pll_m(4:0) and gcm6.pll_n(5:0) which is used in asynchronous micro controller modes.
data sheet 41 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description 3 functional description 3.1 hardware the octalliu tm always requires two supply voltages, 1.8 v and 3.3 v. 3.2 software the octalliu tm device contains analog and digital function blocks that are configured and controlled by an external microprocessor or micro controller, using either the asynchronous interface, spi bus or sci bus. the register address range is 11 bit wide. 3.3 functional overview the main interfaces are receive and transmit line interface asynchronous microprocessor interface with two modes: intel or motorola spi bus interface sci bus interface framer interface boundary scan interface as well as several control lines for reset, mode and clocking purpose. the main internal functional blocks are analog line receiver with equalizer network and clock/data recovery analog line driver with programmable pulse shaper and line build out master clock generation unit dual elastic buffers for receive and transmit direction, controlled by the appropriate jitter attenuators receive line decoding, alarm detection and prbs monitoring transmit line encoding, alarm and prbs generation receive jitter attenuator transmit jitter attenuator available test loops: local loop, remote loop and payload loop boundary scan control
octalliu tm pef 22508 e functional description data sheet 42 rev. 1.0, 2005-06-02 3.4 block diagram figure 5 shows the block diagram of the octalliu tm . figure 5 block diagram 3.5 functional blocks the four possible micro controller interface modes - two asynchronous modes (intel, motorola) and two serial interface modes (spi bus or sci bus) - are selected by using the interface mode selection pins im(1:0). this selection is valid immediately after reset becomes inactive. after changing of the interface mode by im(1:0), a hardware reset must be applied. 3.5.1 asynchronous micro controller in terface (intel or motorola mode) the asychronous micro controller interface is selected if im(1:0) is strapped to 00b (intel mode) or 01b (motorola mode). an handshake signal (data acknowledge dtack for motorola- and ready for intel-mode) is provided indicating successful read or write cycle. by using dtack or ready respectively no counter is necessary in the micro controller to finish the access, see also timing diagrams figure 43 ff. the generation of ready is asynchronous: in intel mode read access ready will be set to low by the octalliu tm after the data output is stable at the octalliu tm . after the rising edge of rd (which is driven by the micro controller), ready is low for a ?hold time?, before it will be set to high by the octalliu tm . in the intel mode write access ready will be set to low by the octalliu tm after the falling edge of wr (which is driven by the micro controller). after wr is high and data are written successfully into the registers of the octalliu tm , ready will be set to high by the octalliu tm . the general timing diagrams are shown in figure 43 to figure 48 . long+shor t haul receive line interface long+shor t haul tr ansmi t line interface clock & data recovery local l oop remote loo p + jatt li ne decoder prbs monitor dual recei ve elastic buffer dual tr ansmi t elastic buffer transmit ji tter attunator receive jitter attunator mux mux receive fr amer interface tr ansmi t fr amer interface fclkx( 1:8) tclk rclk xdi( 1:8) xpa( 1:8) xpb( 1:8) rpa(1:8) rpb(1:8) rpc(1:8) rdo(1:8) fclkr( 1:8) xl1/xoid( 1:8) xl2( 1:8) rl1/roid(1:8) rl2( 1:8) 1 ? 8 boundar y scan jtag asynchr onous mi cr o contr ol l er inter face spi interface sci interface master cl ocki ng unit mclk sync fsc tdi,tms,tck,trs,tdo d(15:0) a( 10:0) cs wr / r w rd/ds bhe/ble ale dbw res int ready/tdack im(1:0) xl3( 1:8) xl4( 1:8) rls(1:8) li ne encoder prbs gener. ibl monitor ibl gener ator oct alli u_blockdiagram p ayl oad loop
data sheet 43 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description the communication between the external micro controller and the octalliu tm is done using a set of directly accessible registers. the interface can be configured as intel or motorola type with a selectable data bus width of 8 or 16 bits. the external micro controller transfers data to and from the octalliu tm , sets the operating modes, controls function sequences, and gets status information by writing or reading control and status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe / ble as shown in table 3 and table 4 . table 5 shows how the ale ( a ddress l atch e nable) line is used to control the bus structure and interface type. the switching of ale allows the octalliu tm to be directly connected to a multiplexed address/data bus. 3.5.1.1 mixed byte/word access reading from or writing to the internal registers can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access is allowed without any restrictions. the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected asynchronous microprocessor interface mode: table 3 data bus access (16-bit intel mode) bhe a0 register access octalliu tm data pins used 0 0 register word access (even addresses) d(15:0) 0 1 register byte access (odd addresses) d(15:8) 1 0 register byte access (even addresses) d(7:0) 1 1 no transfer performed none table 4 data bus access (16-bit motorola mode) ble a0 register access octalliu tm data pins used 0 0 register word access (even addresses) d(15:0) 0 1 register byte access (odd addresses) d(7:0) 1 0 register byte access (even addresses) d(15:8) 1 1 no transfer performed none table 5 selectable asynchronous bus and microprocessor interface configuration ale im(1:0) asynchronous microprocessor interface mode bus structure constant level 01 motorola de-multiplexed 00 intel de-multiplexed switching 00 intel multiplexed
octalliu tm pef 22508 e functional description data sheet 44 rev. 1.0, 2005-06-02 n: even address 3.5.2 serial micro controller interfaces two serial interfaces are included to enable device programming and controlling:- slave serial control interface (sci) - slave serial peripheral interface (spi) by using the sci interface, the octalliu tm can be easily connected to infineon interworking devices plus infineon shdsl- and adsl-phys so that implementation of different line transmission technologies on the same line card easily is possible. the sci interface is a three-wire bus and optionally replaces the parallel processor interface to reduce wiring overhead on the pcb, especially if multiple devices are used on a single board. data on the bus is hdlc encapsulated and uses a message-based communication protocol. if sci interface with multipoint to multipoint configuration is used, address pins a(5:0) are used for sci source (slave) address pin strapping, see table 2 . note that after a reset writing into or reading from octalliu tm registers using the sci- or spi-interface is not possible until the pll is locked: if the sci-interface is used no acknowledge message will be sent by the octalliu tm . if the spi-interface is used pin sdo has high impedance (sdo is pulled up by external resistor). to trace if the spi interface is accessible, the micro controller should poll for example the register dstr so long as it read no longer the value f h . 3.5.2.1 sci interface the serial control interface (sci) is selected if im(1:0) is strapped to 11 h . the octalliu tm sci interface is always a slave. figure 49 shows the timing diagram of the sci interface, table 56 gives the appropriate values of the timing parameters. figure 6 shows a first application using the sci interfaces of some octalliu tm s where point to point full duplex connections are realized between every octalliu tm and the micro controller. here the data out pins of the sci interfaces (sci_txd) of the octalliu tm s must be configured as push-pull (pp), see configuration register bit pp in table 8 . figure 7 shows an application with multipoint to multipoint connections between the octalliu tm s and the micro controller (half duplex). here the data out pin of the sci interfaces (sci_txd) of all octalliu tm s must be configured as an open drain (od), see configuration register bit pp in table 8 . the data out and data in pins (sci_rxd, sci_txd) of each octalliu tm are connected together to form a common data line. together with a common pull up resistor for the data line, all open drain data out pins are building a wired and. the infineon proprietary daisy-chain approach is not supported the group address of the sci interface is 00 h after reset. recommendation for configuring is c4 h to be different to the group addresses of all other infineon devices. in case of multipoint to multipoint applications the 6 msbs of the sci source address will be defined by pinstrapping of the address pins a5 to a0. the two lsbs of the sci source address are constant 10b, see table 8 . the sci source address can be overwritten by a write command into the sci configuration register. for applications with point to point connections for the sci interface the source address is not valid. because 14 bits are used for the register addresses in the sci interface macro the two msbs of the 16 bit wide register addresses are set fixed to zero. intel (address n + 1) (address n) motorola (address n) (address n + 1) data lines d15 d8 d7 d0
data sheet 45 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 6 sci interface application with point to point connections figure 7 sci interface application with mu ltipoint to multipoint connection the following configurations of the sci interface of the octalliu tm can be set by the micro controller by a write command into the sci configuration register (control bits 10 b , see table 8 , sci register address is 0000 h , see table 3 and figure 9 ): half duplex/full duplex (reset value: half duplex), bit dup. opendrain/push-pull (configuration of output pin to opendrain/push-pull is in general independent of the duplex mode and must be set appropriately in application) (reset value: open drain), bit pp. crc for transmit and receive on/off (reset value: off), bit crc_en. automatic acknowledgement of cmd messages on/off (reset value: off), bit ack_en. clock edge rising/falling (reset value: falling), bit clk_pol. clock gating (reset value: off), bit clk_gat. the following sci configurations are fixed and cannot be set by the micro controller: interrupt feature is disabled, bit int_en = 0 b . arbitration always made with lapd (only sci applications like in figure 6 and figure 7 are possible), bit arb = 0 b . the maximum possible sci clock frequency is 6 mhz for point to point applications (full duplex) and about 2 mhz for multipoint to multipoint applications, dependent on the electrical capacity of the bus lines of the pcb. figure 8 shows the message structure of the octalliu tm . the sci interface uses hdlc frames for communication. the hdlc flags mark beginning and end of all messages. microprocessor or interworking device im(1:0) im(1:0) im(1:0) txdata rxdat a clk txdata rxdat a clk txdata rxdat a clk octalliu sci_txd sci_rxd pp octalliu octalliu octalliu-interfaces_2 mi cr o- pr ocessor or interworking device im(1:0) im(1:0) im(1:0) clk clk clk oct alli u_sci _half duplex a(5:0) a(5:0) a(5:0) sci _rxd od octal liu sci _txd dat a dat a dat a octal liu octal liu
octalliu tm pef 22508 e functional description data sheet 46 rev. 1.0, 2005-06-02 figure 8 sci message structure of octalliu tm every write into or read from a register of the octalliu tm is initiated by a command message cmd from the host (micro con roller) and is then confirmed by an acknowledge message ack from the octalliu tm if in the sci configuration automatic acknowledgement is set (bit ack_en, see table 8 ). the frame structure of this messages are shown in figure 9 . in general the lsb of every byte is transmitted first and lower bytes are transmitted before higher bytes (regarding the register address) source and destination addresses are 8 bits long. only the first 6 bits are really used for addressing. the bit c/r (command/response) distinguishes between a command and a response. the bit ms (master/slave) is 0 b for all slaves and 1 b for all masters, see table 8 and figure 9 the source address is defined by pinstrapping of a5 to a0 after reset, but other values can be configured by programming of the sci configuration register. the payload of the write cmd includes two control bits (msbs of the payload), which distinguish between the different kind of commands, see table 7 , the 14 bit wide register address and the 8 bit wide data whereas the read cmd payload includes only the control bits and the register address. register addresses can be either octalliu tm register addresses or sci configuration register addresses. because of the address space of the octalliu tm , really 11 lsbs of the 14 bit address are used in the octalliu tm . the 3 msbs are ignored the frame check sequence fcs has16 bits the read status byte rsta of the acknowledge message shows the status of the received message and is built by the sci interface of the octalliu tm , see figure 11 and table 6 . the destination address in the ack message is always the source address of the corresponding cmd (the address of the micro controller), see figure 10 , because no cmd messages will be sent by the octalliu tm sci interface host octalliu cmd ack octalliu_sci_message_structur e
data sheet 47 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 9 frame structure of octalliu tm sci messages figure 10 principle of building addresses and rsta bytes in the sci ack message of the octalliu tm flag address octalliu_sci_frame_structur e flag fcs sci hdlc basic frame structure 01111110 source address 14 bit register address 01111110 fcs write cmd frame structure destination address 8 bit data 00: write octalfalc register 10: write sci configuration register 01111110 source address rsta 01111110 destination address write ack frame structure payload 01111110 source address 01111110 fcs read cmd frame structure destination address 01: read octalfalc register 11: read sci configuration register 6 bit address c/r ms lsb 14 bit register address control bits t read depth fcs 01111110 source address rsta 01111110 register content destination address fcs one byte read ack frame structure octalliu_sci_acknowledg e source address rsta destination address ack source address cmd destination address octalliu sci interface rsta register source address
octalliu tm pef 22508 e functional description data sheet 48 rev. 1.0, 2005-06-02 figure 11 read status byte (rsta) by te of the sci acknowledge (ack) 3.5.2.2 spi interface the serial peripheral interface (spi) is selected if im(1:0) is strapped to 10 h . the spi interface of the octalliu tm is always a slave. table 6 read status byte (rsta) byte of the sci acknowledge (ack) field bit description vfr 7 valid frame. indicates whether a valid frame has received. 0 b : received frame is invalid. 1 b : received frame is valid. rdo 6 reserved crc 5 crc compare check. indicates whether a crc check is failed or not. 0 b : crc error check failed on the received frame. 1 b : received frame is free of crc errors. rab 4 received message aborted. cmd message abortion is declared. the receive message was aborted by the host. a sequence of 7 consecutive 1 was detected before closing the flag. note that ack message and therefore rab will not be send before destination address was received. 0 b : data reception is in progress. 0 b : data reception has been aborted. sa1 3 reserved sa0 2 reserved c/r 1 reserved ta 0 reserved table 7 definition of control bits in commands (cmd) control bits (msb lsb) command type 01 read octalliu tm registers 00 write octalliu tm register1 10 write sci configuration register 11 read sci configuration register table 8 sci configuration register content address bit 7 (msb) bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h pp clk_pol clk_gat ack_en int_en crc_en arb dup 0001 h 1 destination address 1 (=c/r) 0 (=ms) 0002 h 0 group address 1 (=c/r) 0 (=ms) vfr rdo octalfalc_sci_rst a ta c/r sa0 sa1 rab crc 7 (msb) 0 (lsb)
data sheet 49 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 12 and figure 13 show the read and the write operation respectively. the start of a read or write operation is marked by the falling edge of the chip select signal cs whereas the end of the operations is marked by the rising edge of cs. because of cs the spi interface has no slave address. the first bit of the serial data in (sdi) is 1 for a read operation and 0 for a write operation. the first four bits of the 15-bit address are not valid for the octalliu tm . in read operation the octalliu tm delivers the 8 bit wide content of the addressed register at the serial data out (sdo). in general spi data are driven with the negative edge of the serial clock (sclk) and sampled with the positive edge of sclk. figure 50 shows the timing of the spi interface and table 57 the appropriate timing parameter values. figure 12 spi read operation figure 13 spi write operation 3.5.3 interrupt interface special events in the octalliu tm are indicated by means of an interrupt output int, which requests the external micro controller to read status information from the octalliu tm , or to transfer data from/to the octalliu tm . the electrical characteristics (open drain or push-pull) is programmed defined by the register bits ipc.ic(1:0), see ipc . the octalliu tm has a single interrupt output pin int with programmable characteristics (open drain or push-pull, defined by registers ipc) too. since only one int request output is provided, the cause of an interrupt must be determined by the external micro controller by reading the octalliu tm ?s interrupt status registers (gis, isr(1:4), isr6 and isr7). the interrupt on pin int and the interrupt status bits are reset by reading the interrupt status registers. the interrupt status registers isr are of type ?cl ear on read? (?rsc?). the structure of the interrupt status registers is shown in figure 14 . o ct al_falc_spi _read cs sclk xx x x a10 a0 d7 d0 11 bi t addr ess 8 bi t data sdi don t care hi gh i mpedance sdo o ct al_falc_spi _writ e cs sclk xx x x a10 a0 d7 d0 11 bi t addr ess 8 bi t data sdi hi gh i mpedance sdo
octalliu tm pef 22508 e functional description data sheet 50 rev. 1.0, 2005-06-02 figure 14 interrupt status registers each interrupt indication bit of the registers isr can be selectively masked by setting the corresponding bit in the corresponding mask registers imr. if the interrupt status bits are masked they neither generate an interrupt at int nor are they visible in isr. all reserved bits in the mask registers imr must not be written with the value 0. gis, the non-maskable ?global? interrupt status register per channel, serves as pointer to pending interrupts sourced by registers isr(1:4), isr6 and isr7. the non-maskable channel interrupt status register cis serves as channel pointer to pending interrupts sourced by registers gis. after the octalliu tm has requested an interrupt by activating its int pin, the external micro controller should first read the register cis to identify the requesting interrupt source channel. then it should read the global interrupt status register gis to identify the requesting interrupt source register isr of that channel. after reading the assigned interrupt status registers isr(1:4), isr6 and isr7, the pointer bit in register gis is cleared or updated if another interrupt requires service. after all bits isr(7:0) of a register gis are cleared, the assigned bit in register cis is cleared. after all bits in register cis are cleared the int pin will be deactivated. if all pending interrupts are acknowledged by reading (gis is reset), pin int goes inactive. updating of interrupt status registers isr(1:4), isr6 and isr7 and gis is only prohibited during read access. ?global? interrupt status register gis (per channel) imr1 isr1 imr3 isr3 imr4 isr4 oct alli u_i sr_2 imr6 isr6 imr7 isr7 gis4 gis1 gis2 gis3 status regi ster s and maski ng ( shown for one channel ) channel interrupt status register cis , global channel channel ... di ffer ent status bi ts ... ... ... ... ... int channel gis8 gis7 gis6 gis5 . . . 1 to 8 .. . 1 to 8 pll plllc plll gis2 gimr pllls not visible vis gcr vispll ipc isr1 isr3 isr4 isr6 isr7 isr1 isr3 isr4 isr6 isr7 imr2 isr2 ... isr2 r2
data sheet 51 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description masked interrupts visible in status registers the ?global? interrupt status register (gis) indicates those interrupt status registers with active interrupt indications (bits gis.isr(7:0)). an additional interrupt mode can be selected per port via bit gcr.vis ( gcr ). in this mode, masked interrupt status bits neither generate an interrupt on pin int nor are they visible in gis, but are displayed in the corresponding interrupt status registers isr(1:4), isr6 and isr7. pll interrupt status register the bit n (n = 1 to 8) of the register cis pointers an interrupt on channel n. the global interrupt status register gis2 indicates the lock status of the (global) pll. masking can be done by the register gimr. an additional interrupt mode can be selected per port via bit ipc.vispll ( ipc ) where the masked interrupt status bit gis2.pllls does not generate an interrupt on pin int, but is displayed in the corresponding interrupt status register bit gis2.plllc . the additional interrupt mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. note: 1. in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. 2. all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no ?hierarchical? polling possible), since gis only contains information on actually generated, i.e. unmasked interrupts. 3.5.4 boundary scan interface in the octalliu tm a t est a ccess p ort (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard ieee 1149.1-2001. figure 15 gives an overview, figure 41 shows the timing diagram and table 52 gives the appropriate values of the timing parameters. table 9 interrupt modes gcr.vis; ipc.vispll appropriate mask bit interrupt active visibility in isr(1:4), isr(6:7) and gis2 0 0 yes yes 0 1 no no 1 0 yes yes 1 1 no yes
octalliu tm pef 22508 e functional description data sheet 52 rev. 1.0, 2005-06-02 figure 15 block diagram of test access port and boundary scan after switching on the device (power-on), a reset signal has to be applied to trs , which forces the tap controller into test logic reset state. for normal operation without boundary scan access, the boundary reset pin trs can be tied to the device reset pin res . the boundary length is 247. if no boundary scan operation is used, trs has to be connected to rst or v ss . tms, tck and tdi do not need to be connected since pull-up transistors ensure high input levels in this case. test handling (boundary scan operation) is performed using the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output) when the tap controller is not in its reset state, that means trs is connected to v dd or it remains unconnected due to its internal pull up. test data at tdi is loaded with a clock signal connected to tck. "1" or "0" on tms causes a transition from one controller state to another; constant "1" on tms leads to normal operation of the chip. an input pin (i) uses one boundary scan cell (data in), an output pin (o) uses two cells (data out and enable) and an i/o-pin (i/o) uses three cells (data in, data out and enable). note that most functional output and input pins of the octalliu tm are tested as i/o pins in boundary scan, hence using three cells. the desired test mode is selected by serially loading a 8-bit instruction code into the instruction register through tdi (lsb first), see table 10 . the test modes are: extest extest is used to examine the interconnection of the devices on the board. in this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values ("0" or "1"). then the contents of the boundary scan is shifted to tdo. at the same time the next scan vector is loaded from tdi. subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. f0115 trs tck tms tdi tdo clock test control data in enable data out clock generation reset tap controller finite state machine instruction register test signal generator tap controller reset identification register (32 bits) control bus boundary scan (n bits) 1 2 n bd data in bd data out id data out
data sheet 53 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description sample is a test mode which provides a snapshot of pin levels during normal operation. idcode a 32-bit identification register is serially read out on pin tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". the id code field is set to (msb to lsb): 0001 0000 0000 1101 1110 0000 1000 0011 b . version number (first 4 bits) = 0001 b part number (next 16 bits) = 0000 0000 1101 1110 b manufacturer id (next 11 bits) =0000 1000 001 b lsb fixed to 1. bypass a bit entering tdi is shifted to tdo after one tck clock cycle. an alphabetical overview of all tap controller operation codes is given in table 10 . 3.5.5 master clocking unit the octalliu tm provides a flexible clocking unit, which references to any clock in the range of 1.02 to 20 mhz supplied on pin mclk, see figure 16 . the clocking unit has two different modes: in the so called ?flexible master clocking mode? (gcm2.vfreq_en = 1, cmr2 ) the clocking unit has to be tuned to the selected reference frequency by setting the global clock mode registers gcm(8:1) accordingly, see formulas in gcm6 . all eight ports can work in e1 or t1 mode individually. after reset the clocking unit is in ?flexible master clocking mode?. in the so called ?clocking fixed mode? (gcm2.vfreq_en = 0) the tuning of the clocking unit is done internally so that no setting of the global clock mode registers gcm(8:1) is necessary. all eight ports must work together either in e1 or in t1 mode. for the calculation for the appropriate register settings see gcm6 . calculation can be done easy by using the flexible master clock calculator which is part of the software support of the octalliu tm , see chapter 8.3 . all required clocks for e1 or t1/j1 operation are generated by this circuit internally. the global setting depends only on the selected master clock frequency and is the same for e1 and t1/j1 because both clock rates are provided simultaneously. to meet the e1 requirements the mclk reference clock must have an accuracy of better than 32 ppm. the synthesized clock can be controlled on pins rclk and fclkr. table 10 tap controller instruction codes tap instruction instruction code bypass 11111111 extest 00000000 idcode 00000100 sample 00000001 reserved for device test 01010011
octalliu tm pef 22508 e functional description data sheet 54 rev. 1.0, 2005-06-02 figure 16 flexible master clock unit 3.5.5.1 pll (reset and configuring) if the (asynchronous) micro controller interface mode is selected by im(1:0) the pll must be configured by programming of the registers gcm5 and gcm6 in ?flexible master clocking mode?. every change of the contents of these registers - the divider factors n and m of the pll - causes a reset of the pll. switching between e1 and t1 modes in arbitrary channels causes a reset of the clock unit but not of the pll itself. or by enabling of the ?fixed mode?: gcm2.vfreq_en = 0 ( gcm2 ). programming of registers gcm5 and gcm6 is not necessary. any programming of gcm5 and gcm6 does not cause a reset of the pll. switching between e1 and t1 modes (for all channels) causes a reset of the clock unit but not of the pll itself. the spi and sci are synchronous interfaces and therefore need defined clocks immediately after reset, before any configuration is done. so to enable access to serial interfaces, the clock mclk must be active and must have a defined frequency before reset becomes inactive. dependent on the mclk frequency the internal pll must be configured if the sci- or spi-interface mode is selected by im(1:0) by strapping of the pins d(15:5) if ?fixed mode? is not enabled (gcm2.vfreq_en = 1), see also table 2 . because ?fixed mode? is not enabled after reset, pinstrapping at d(15:5) is always necessary! every new value at this pins causes a reset of the pll. configuring by the registers gcm5 and gcm6 is not taken into account and causes not a reset of the pll or by enabling of the ? fixed mode?.this is only allowed if the values of n and m defined by pinstrapping are identical to that values which are internally used for the ?fixed mode?. that avoids changing of n and m by switching into the ?fixed mode? and therefore a new reset of the pll. (a new reset of the pll can cause a hang up of the whole system!) in ?fixed mode? the values are: n = 33 10 , m = 0 10 so that the pinstrapping must be: d(10:5) = hllllh, d(15:11) = lllll. in ?fixed mode? programming of registers gcm1 to gcm8 is no longer necessary and values at the pins d(15:5) are no longer taken into account and causes not a reset of the pll. a switching between e1 and t1 modes causes a reset of the clock unit but not of the pll itself. the configuration of the pll by pinstrapping (see table 2 ) in case of serial interface modes is done in the same way as by using the registers gcm5 and gcm6 if asynchronous micro controller interface mode (intel or motorola) is selected. so calculation of the pinstrapping values can be done also by using the formulas in gcm6 or by using the ?flexible master clock calculator? which is part of the software support of the octalliu tm , see chapter 8.3 . if the serial interfaces are selected, pinstrapping of d(15:5) configure the pll directly, so changes causes always a reset of the pll. the conditions to trigger a reset of the central clock pll are listed in table 11 . every reset of the pll causes a reset of the clock system. flexible master clock unit gcm1...gcm8 mclk e1 clocks t1 / j1 clocks octal falc __f011 6 pll channel 1 to 8 im(1:0) d(15:5)
data sheet 55 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description 3.6 line coding and framer interface modes an overview of the coding at the line interface and the modes at the framer interface is given in table 12 . table 11 conditions for a pll reset reset pin gcm2.vfreq_en used controller interface a pll reset is made if ... active x (will be set to 1 by reset) x always inactive 1 asynchron (motorola or intel) if gcm5 or gcm6 are written and their values n or m change spi or sci if pinstrapping values change 0 asynchron (motorola or intel) never spi or sci if pinstrapping values change 0 -> 1 or 1 -> 0 asynchron (motorola or intel) if actual values of n or m in gcm5 or gcm6 are different to internal settings of the ?clocking fixed mode? spi or sci if pinstrap values are different to internal settings of the ?clocking fixed mode?; that is not allowed! table 12 line coding and framer interface modes line code, framer if mode register bits signals at pins fmr0.rc, lim3.drr fmr0.xc, lim3.drx rdon (rpc) rdo xdi xdin (xpb) ami, single rail 10 0 10 0 pos and neg ami error pos, via encoder neg, via encoder ami, dual rail 10 1 10 1 pos neg pos, encoder bypass neg, encoder bypass hdb3/b8zs, single rail 11 0 11 0 decoded data violation via encoder (hdb3/b8z s coding) hdb3/b8zs, dual rail 11 1 11 1 pos neg via encoder (hdb3/b8z s coding) nrz, single rail 00 0 00 0 pos 0 nrz, via encoder frame marker nrz, dual rail 00 1 00 1 pos neg nrz frame marker cmi, single rail 01 0 01 0 decoded data violation via encoder (cmi coding) cmi, dual rail 01 1 01 1 pos neg via encoder (cmi coding)
octalliu tm pef 22508 e functional description data sheet 56 rev. 1.0, 2005-06-02 3.7 receive path an overview about the receive path of one channel of the octalliu tm is given in figure 17 . figure 17 receive system of one channel the recovered clock selection of figure 17 (multiplexer ?a?) is shown in more detail in figure 18 . the multiplexer ?c? in figure 17 selects the mode of the receive jitter attenuator, see chapter chapter 3.7.9 . the multiplexer ?d? in figure 17 selects if the receive clock rclk of a channel is sourced by the recovered route clock or by the dco-r (see above). the appropriate control register bits are cmr4.rs(2:0) ( cmr4 ). these register bits selects also different dco-r output frequencies. the sources of the receive clock output pins of the octalliu tm (rclk(8:1)), can be selected out of the receive clocks of the channels: the source of each of the eight receive clock pins of the octalliu tm (rclk(8:1)) can be independently selected out of each of the eight receive clocks of the channels by programming the registers bits gpc(2:6).rs(2:0) ( gpc2 ), see cross connection ?b? in figure 18 . 0 -> 1 or 1 -> 0 asynchron (motorola or intel) if actual values of n or m in gcm5 or gcm6 are different to internal settings of the ?clocking fixed mode? spi or sci if pinstrap values are different to internal settings of the ?clocking fixed mode?; that is not allowed! table 12 line coding and framer interface modes (cont?d) line code, framer if mode register bits signals at pins fmr0.rc, lim3.drr fmr0.xc, lim3.drx rdon (rpc) rdo xdi xdin (xpb) octalliu _f0117 a: contr ol l ed by cmr5.drss( 2:0) c: controlled by cmr1.dcs and lim0.mas d: controlled by cmr4.rs(2:0) j: controlled by cmr2.irsc and dic1.rbs(1:0) alarm detector analog los detector rclk sync rl1/roid rl2 dco-r mclk recovered clock selection fr om other channel s recei ve li ne interface a c d master clocking unit los j fclkr internal receive clock ... equalizer cl ock & data recovery decoder rdo dual receive elastic buffer dpll rdon
data sheet 57 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 18 recovered and receive clock selection 3.7.1 receive line interface for data input, two different data types are supported (see also table 12 ): ternary coded signals received at pins rl1 and rl2 from 0 db downto -43 db for e1 or downto -36 db for t1/j1 ternary interface. the ternary interface is selected if lim1.drs is cleared. unipolar data (cmi code) on pin roid received from an optical interface. the optical interface is selected if lim1.drs is set and mr0.rc(1:0) = 01 b . 3.7.2 receive line coding in e1 applications, hdb3 line code and ami coding is provided for the data received from the ternary interface. in t1/j1 mode, b8zs and ami code is supported. selection of the receive line code is done with register bits mr0.rc(1:0) ( mr0 ). in case of the optical interface the cmi code (1t2b) with hdb3 or ami postprocessing is provided. if cmi code is selected the receive route clock is recovered from the data stream. the cmi decoder does not correct any errors. the hdb3 code is used along with double violation detection or extended code violation detection (selectable by mr0.exze)). in ami code all code violations are detected. the detected errors increment the code violation counter (16 bits length). the signal at the ternary interface is received at both ends of a transformer. an overview of the receive line coding is given in table 12 . 3.7.3 receive line termi nation (analog switch) in general the e1 line impedance operating modes with 75 ? (used with coaxial cable) or with 120 ? (used with twisted pair cable) line termination are selectable by switching resistors in parallel or using special transformers with different transfer ratios in one package (using center tap). these two options both provide only one analog front end circuitry for both transmission media types. the octalliu tm supports a software selectable generic e1/t1/j1 solution without the need for external hardware changes by using the integrated analog switch and two external resistors for line impedance matching, see application example in figure 19 . by default the analog switch is off. this allows, for example, to switch between 100 w (t1/e1 twisted pair) and 75 w (e1 coax) termination resistance using the external resistors r e1 = 100 ? and r e2 = 300 ? , see table 13 . the analog switch can be controlled by access to the register bit lim0.rtrs ( lim0 ) and by hardware using the receive multi function ports. for that, only sync octal falc _rec_clk_sel_2 receive clock selection to dco_r recovered clock selection to dco_r channel 1 channel 2 rclk1 b a: contr oll ed by cmr5.drss( 2:0) b: contr oll ed by gpc( 2:6) .rs( 2:0) to dco_r channel 4 c c c rclk rclk rclk ... rclk7 rclk4 rclk5 rclk8 rclk6 rclk3 rclk2 a a a pins recovered clock selection recovered clock selection
octalliu tm pef 22508 e functional description data sheet 58 rev. 1.0, 2005-06-02 one (but not more) of the receive multi function ports must be configured as receive line termination (rlt) input. for controlling of the analog switch a logical equivalence is build out of rlt and the register bit lim0.rtrs if rlt is configured at one multi function port. if the analog switched is not used in an application, the pin rls can be left open. figure 19 receiver configuration with integrated analog switch for receive impedance matching 3.7.4 receive line monitoring mode for short-haul applications like shown in figure 20 , the receive equalizer can be switched into receive line monitoring mode (lim0.rlm = 1). one channel is used as a short-haul receiver while the other is used as a short-haul monitor. in this mode the receiver sensitivity is increased to detect an incoming signal of -20 db resistive attenuation. the required resistor values are given in table 14 . figure 20 receive line monitoring rlm (shown for one line) table 13 receiver configuration examples line impedance z 0 external resistor r e1 external resistor r e2 internal analog switch lim0.rtrs; rlt 120 ? 100 ? (for common e1/t1/j1 applications) 300 ? (for common e1/t1/j1 applications) off if rlt is configured: (lim0.rtrs equivalent rlt) = 0 if rlt is not configured: lim0.rtrs = 0 100 ? off 75 ? on if rlt is configured: (lim0.rtrs equivalent rlt) = 1 if rlt is not configured: lim0.rtrs = 1 internally exter nal ly r e1 rl1 rl2 z 0 rls r e2 anal og switch octalliu tm (receiver channel) octalliu tm (monitor channel) rl1 e1/t1/j1 receive line lim0.rlm=0 lim0.rlm=1 r1 r2 r3 r3 rl2 rl1 rl2 t2 : t1 t2 : t1 resistive -20 db network octalliu _f0074
data sheet 59 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description using the receive line monitor mode and the hardware tristate function of transmit lines xl1/2 on the line side and the tristate functions on the framer side, the octalliu tm supports applications connecting two channels to one receive and transmission line. in these kind of applications both channels are working in parallel for redundancy purpose (see figure 21 ). while one of them is driving the line, the other one must be switched into transmit line tristate mode. if both channels are configured identically and supplied with the same system data and clocks, the transmit path can be switched from one channel to the other without causing a synchronization loss at the remote end. figure 21 redundancy application using rlm (shown for one line) rdop and fclkr can be set into tristate mode constantly for redundancy applications using the register bit dic3.rrtri ( dic3 ) and - if the rtdmt function is selected on one of the multi function port - by rtdmt, see chapter 3.12 . if the rtdmt function is selected the values of rtdmt and dic3.rrtri are logically exored. this enables an easy redundancy application using only one signal for switching between two devices. if the rtdmt function is not selected dic3.rrtri = 1 set the pins into tristate mode constantly. in this mode ?tristate? means high impedance against v dd and v ss : no pull up or pull down resistor is active. table 14 external component recommendations (monitoring) parameter 1) 1) this includes all parasitic effects caused by circuit board design. characteristic impedance (ohm) characteristic impedance (ohm) e1 t1 j1 75 120 100 110 r 1 ( 1 %) ( ? ) 75 120 100 110 r 2 ( 1 %) ( ? ) 75 120 100 110 r 3 ( 1 %) ( ? ) 330 510 430 470 t 2 : t 1 1 :1 1 :1 1 : 1 1 : 1 e1/t1/j1 receive line rl1 rl2 rdop rl1 rl2 rdop xl1 xl2 e1/t1/j1 transmit line xdip xl1 xl2 xdip xlt (xpa) active/stand-by st and- by/act ice fclkr fclkr xlt (xpa) oct alli u_receiver_2 rtdmt rtdmt low/high dic3.rrtri = 0 dic3.rrtri = 1 (rpa) (rpa) fclkx fclkx fr amer 1/8 octalliu tm 1/8 oct alliu tm
octalliu tm pef 22508 e functional description data sheet 60 rev. 1.0, 2005-06-02 an overview about the tristate configurations of rdop and rclk is given in table 15 . switching between both channels can be done on the line side in transmit direction by a hardware signal if the multi function pin xpa is configured as tristate input xlt by the register bits pc1.xpc1 = 1000 b , see pc1 . if one pin xpa is programmed as low active (pc1.xpc1 = 1110 b ) and the one of the other channel as high active (pc1.xpc1 = 1000 b ), no external inverter is necessary as shown in figure 21 . so switching between both channels on line side is possible using only one signal. switching can also be done on the line side in transmit direction by software, if setting the register bit xpm2.xlt. the register bit value xpm2.xlt and the pin value of xpa are logically ord. (that means if xpa is configured as low active then tristate = xpm2.xlt or not(xpa ). because the register bit xpm2.xlt and the multi function pin xpa exist individually for every channel, switching on the line side in transmit direction can be done between channels of different or of the same octalliu tm device switching between both channels can be done on the system side in receive direction by using the register bit dic3.rrtri and with or without selection of the multi function port as rtdmt. if the rtdmt function is selected the values of rtdmt and dic3.rrtri are logically exored. if in one of the both channels dic3.rrtri is set, rtdmt is low active because of the logical exor, and if in the other channel dic3.rrtri is cleared, rtdmt is low active because of the logical exor. so switching between both channels on system (framer) side in receive direction is possible using only one signal. by using the xlt, xlt and rtdmt function of the multi function ports and do the appropriate programming of the bits dic3.rrtri ( dic3 ), switching between both channels can be done on the system and the line side together with only one common signal, connected to xpa (xlt, xlt ) and rpa (rtdmt), as shown in figure 21 and table 16 : if this signal has low-level channel 1 is active and channel 2 is in stand-by, if it has high level channel 1 is in stand-by and channel 2 is active. figure 22 shows a redundancy application for long haul mode using the internal analog switch. with the configuration shown in table 17 , switching between both channels is possible using only one board signal which is connected to xlt, xlt , rlt and rtdmt. because the octalliu tm builds the logical equivalence out of rlt and lim0.rtrs, the analog switches of both channels are controlled by these signal. table 15 tristate configurations for the rdo and rclk pins dic3.rrtri / dic3.rrtri exor rtdmt if rtdmt is selected on multi function port dic3.rtri pin rdop pin fclkx 1 x constant tristate (without pull up and pull down resistor) constant tristate (without pull up and pull down resistor) 0 0 never tristate never tristate 0 1 tristate during inactive channel phases (with pull up resistor never tristate table 16 redundancy application using rlm, switching with only one signal configuration register bits channel 1 (active) channel 2 (stand-by) xlt, xlt pc1.xpc1(3:0) 1000 1110 rtdmt pc1.rpc1(3:0) 1101 1101 receive system interface dic3.rrtri 0 1 rlm mode lim0.rlm 0 1
data sheet 61 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 22 long haul redundancy application using the analog switch (shown for one line) 3.7.5 loss-of-signal detection there are different definitions for detecting loss-of-signal (los) alarms in the itu-t g.775 and ets 300233. the octalliu tm covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable by using register gcr.sci. detection: an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. a pulse with an amplitude less than q db below nominal is the criteria for ?no pulse? in the analog receive interface (lim1.drs = 0) ( lim1 ). the receive signal level q is programmable by three control bits lim1.ril(2:0) see table 50 . the number n can be set by an 8-bit register (pcd). the contents of the pcd register is multiplied by 16, which results in the number of pulse periods, i.e. the time which has to suspend until the alarm has to be detected. the programmable range is 16 to 4096 pulse periods. ets300233 requires detection intervals of at least 1 ms. this time period results always in a lfa (loss of frame alignment) before a los is detected. table 17 redundancy application using the analog switch, switching with only one board signal configuration register bits channel 1 (active/stand-by) channel 2 (stand-by/active) xlt, xlt pc1.xpc1(3:0) 1000 1110 rtdmt pc1.rpc1(3:0) 1101 1101 receive framer interface dic3.rrtri 0 1 rlt pc2.rpc2(3:0) 1000 1000 receive line termination lim0.rtrs 0 0 e1/t1/j1 receive line rl1 rl2 rdop rl1 rl2 rdop xl1 xl2 e1/t1/j1 transmit line xdip xl1 xl2 xdip xlt (xpa) act ive/st and- by st and- by/act ice fclkr fclkr xlt (xpa) oct alli u_receiver_6 rtdmt rtdmt dic3.rrtri = 0 lim0.rtrs = 0 dic3.rrtri = 1 lim0.rtrs = 1 (rpa ) (rpa ) fclkx fclkx fr amer 1/8 oct alliu tm 1/8 oct alliu tm low/high (rp b) rlt (rpb ) rlt rls rls
octalliu tm pef 22508 e functional description data sheet 62 rev. 1.0, 2005-06-02 recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril(2:0)) of the nominal pulse. the value in the 8-bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. if a loss-of-signal condition is detected in long-haul mode, the data stream can optionally be cleared automatically to avoid bit errors before los is indicated. the selection is done by lim1.clos = 1. 3.7.6 receive equalization network the octalliu tm automatically recovers the signals received on pins rl1 and rl2 in a range of up to -43 db for e1 or -36 db for t1/j1. the maximum reachable length with a 22 awg twisted pair cable is about 1500 m for e1 and about 2000m (~6560 ft) for t1. the integrated receive equalization network recovers signals with up to -43 db for e1 or -36 db for t1/j1 of cable attenuation automatically. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak-detected and sliced to produce the digital data stream. the slicing level is software selectable in four steps (45%, 50%, 55%, 67%), see table 50 . for typical e1 applications, a level of 50% is used. the received data is then forwarded to the clock & data recovery unit. each of the octalliu tm line receivers use parameters which are internally stored in a rom. with these parameters the maximum receiver sensitivity is only 33 db in e1 mode. it is also possible to use parameters stored in an internal ram instead of those stored in the internal rom. the ram parameters must be loaded before activation of the lines. the ram is accessible over the micro controller interface in the same way as the octalliu tm registers by using a special ram access mode. all interface modes (motorola, intel, spi or sci) can be used for ram access. the activation of the ram access mode, the load procedure of the ram, the values of the ram parameters and the deactivation of the ram access mode to have access to the registers again are not described in the data sheet of the octalliu tm . the source code for loading the optimal parameters into the ram is available on request. use of these optimal parameters improves the maximum receiver sensitivity to 43 db in e1 mode. 3.7.7 receive line at tenuation indication status register res reports the current receive line attenuation for e1 in a range from 0 to -43 db in 25 steps of approximately 1.7 db each. for t1/j1 in a range from 0 to -36 db in 25 steps of approximately 1.4 db each. the least significant 5-bits of this register indicate the cable attenuation in db. these 5-bits are only valid in combination with the most significant two bits (res.ev(1:0) = 01 b ). 3.7.8 receive clock and data recovery the analog received signal on pins rl1 and rl2 is equalized and then peak-detected to produce a digital signal. the digital received signal on pins rdip and rdin is directly forwarded to the clock & data recovery. the so called dpll (digital pll) of the receive clock & data recovery extracts the route clock from the data stream received at the rl1/2 or roid lines. the clock & data recovery converts the data stream into a dual-rail, unipolar bit stream. the clock and data recovery uses an internally generated high frequency clock out of the master clocking unit based on mclk. the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ui. 3.7.9 receive jitter attenuator the receive jitter attenuator is based on the dco-r (digital clock oscillator, receive) in the receive path. jitter attenuation of the received data is done in the dual receive elastic buffer. the working clock is an internally generated high frequency clock based on the clock provided on pin mclk. the jitter attenuator meets the e1 requirements of itu-t i.431, g. 736 to 739, g.823 and etsi tbr12/13 and the t1 requirements of at&t pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and itu-t i.431, g.703 and g. 824. the internal pll circuitry dco-r generates a "jitter-free" output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock. the receive jitter attenuator can be synchronized
data sheet 63 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description either on the extracted receive clock rclk or on a 2.048 mhz/8 khz or 1.544 mhz/8 khz clock provided on pin sync (8 khz in master mode only). the jitter attenuated dco-r output clock can be output on pin rclk and fclkr. optionally an 8 khz clock is provided on pin sec ? fsc. for jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by the clock & data recovery and are read out with the de-jittered clock sourced by dco-r. if the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed. if the receive elastic buffer is read out with the receive framer clock fclkr, the receive elastic buffer performs a clock adoption from the recovered receive clock to fclkr. the dco-r circuitry attenuates the incoming jittered clock starting at its corner frequency with 20 db per decade fall-off. wander with a jitter frequency below the corner frequency is passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02 ui. the corner frequency of the dco-r can be configured in a wide range, see table 18 and figure 23 . the jitter attenuator pll in the transmit path, so called as dco-x, is equivalent to the dco-r so that the principle for its configuring is the same. after reset the corner frequencies are 2 hz in e1 and 6 hz in t1/j1 mode and can be switched to 0.2 hz in e1 mode or 0.6 hz n t1 mode by setting the register bit lim2.scf for the dco-r or the register bit cmr5.scfx for the dco-x respectively. a logical table builds the integral (i) and proportional (p) parameter for the pi filter of the dco-r or dco-x, see figure 23 . if the register bits cmr2.ecfar or cmr2.ecfax are set for the dco-r or the dco-x respectively, the corner frequencies can be configured in a range between 2 hz and 0.2 hz using the register bits cmr3.cfar(3:0) or cmr3.cfax(3:0) respectively, see cmr3 , cmr4 and cmr5 . a logical table builds the integral and proportional parameter for the pi filter of the dco-r or dco-x out of the settings in cmr3.cfar(3:0) or cmr3.cfax(3:0) respectively. if additionally to cmr2.ecfar or cmr2.ecfax the bit cmr6.dcocompn ( cmr6 ) is set, which is valid for the dco-r and the dco-x, the corner frequencies and attenuation factors can be programmed in a wide range using the register bits cmr3.cfar(3:0) and cmr4.iar(4:0) for the dco-r and cmr3.cfax(3:0) and cmr5.iax(4:0) for the dco-x. the settings in cmr3.cfar(3:0)/cfax(3:0) build the proportional parameter, the settings in cmr4.iar(4:0) and cmr5.iax(4:0) build the integral parameter for the pi filters, independent from another. table 18 overview dco-r (dco-x) programming cmr6.dcocompn cmr2.ecfar (cmr2.ecfax) lim2.scf (cmr6.scfx) cmr3.cfar(3:0) (cmr3.cfax(3:0)) cmr4.iar(3:0) (cmr5.iax(4:0)) corner- frequencies of dco-r (dco-x) e1 / t1 x 0 0 not used not used 2 hz / 6 hz x 0 1 not used not used 0.2 hz / 0.6 hz 0 1 x 7 h 4 h not used 0.2 hz / 0.6 hz 2 hz / 6 hz 1 1 x 0 h ...f h , used as proportional parameter 9 h 8 h 6 h 4 h 00 h ...1f h used as integral parameter 19 h 13 h 12 h 0f h range 0.2 hz ... 20 hz 0.2 hz 0.6 hz 2 hz 6hz
octalliu tm pef 22508 e functional description data sheet 64 rev. 1.0, 2005-06-02 figure 23 principle of configuring the dco-r and dco-x corner frequencies the dco-r reference clock is watched: if one, two or three clock periods of the 2.048 mhz (1.544 mhz in t1/j1 mode) clock at pin sync or rclki (in single rail digital line interface mode) are missing the dco-r regulates its output frequency. if four or more clock periods are missing the dco-r circuitry is automatically centered to the nominal bit rate if the center function of dco-r is enabled by cmr2.dcf = 0. the actual dco-r output frequency is ?frozen? if the center function of dco-r is disabled by cmr2.dcf = 1. the receive jitter attenuator works in two different modes, selected by the multiplexer ?c? in figure 17 : slave mode: in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of loss of signal (los) the dco-r switches automatically to master mode. the frequency at the pin sync must be 2.048 mhz (1.544 mhz). if bit cmr1.dcs is set automatic switching from the recovered route clock to sync is disabled. master mode: in master mode (lim0.mas = 1) the dco-r is in free running mode if no clock is supplied on pin sync. if an external clock on the sync input is applied, the dco-r synchronizes to this input. the external frequency can be 2.048 mhz (1.544 mhz) for ipc.ssyf = 0 or 8.0 khz for ipc.ssyf = 1. the following table table 19 shows this modes with the corresponding synchronization sources. cmr2 cmr3 cmr6 ? cor ner fr equency adj ust? dco-r (dco-x) ecfax for dco-x, ecfar for dco-r mux reset table oct alli u_dco_x_adjust _2 cfax (for dco- x) cfar ( for dco- r) lim2.scf for dco-r, cmr6.scfx for dco-x switches cor ner fr equency to 0.2 hz i n e1 cor ner fr equency 2 or 0.2 hz in e1 sets corner fr equency to 2 hz i n e1 mux iax ( for dco- x) corner fr equency r ange 2 ? 0.2 hz i n e1 lim2, cmr6 table iar (for dco-r) cmr5 cmr4 dcocomp n cor ner fr equency r ange 8 ? 0.2 hz pi pi p i pi pi
data sheet 65 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description the receive clock output rclk of every channel can be switched between 2 sources, see multiplexer ?d? in figure 17 : if the dco-r is the source of rclk the following frequencies are possible: 1.544, 3.088, 6.176, and 12.352 in t1/j1 mode and 2.048, 4.096, 8.192, and 16.384 mhz in e1 mode. controlling of the frequency is done by the register bits cmr4.rs(1:0). if the recovered clock out (of the clock and data recovery) is the source of rclk (see multiplexer ?d? in figure 17 ), only 2.048 mhz (1.544 mhz) is possible as output frequency. 3.7.9.1 receive jitter attenuation performance for e1 the jitter attenuator meets the jitter transfer requirements of the itu-t i.431 and g.735 to 739 (refer to figure 24 ) for t1/j1 the jitter attenuator meets the jitter transfer requirements of the pub 62411, pub 43802, tr- tsy 009,tr-tsy 253, tr-tsy 499 and itu-t i.431 and g.703 (refer to figure 25 ). table 19 clocking modes of dco-r mode internal los active sync input system clocks generated by dco-r master independent fixed to v dd dco-r centered, if cmr2.dcf = 0. (cmr2.dcf should not be set), see also cmr2 master independent 2.048 mhz (e1) or 1.544 mhz (t1) synchronized to sync input (external 2.048 mhz or 1.544 mhz, ipc.ssyf = 0), see also ipc master independent 8.0 khz synchronized to sync input (external 8.0 khz, ipc.ssyf = 1, cmr2.dcf = 0) slave no fixed to v dd synchronized to recovered line clock slave no 2.048 mhz (e1) or 1.544 mhz (t1) synchronized to recovered line clock slave yes fixed to v dd cmr1.dcs = 0: dco-r is centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) cmr1.dcs = 1: synchronized on recovered line clock slave yes 2.048 mhz cmr1.dcs = 0: synchronized to sync input (external 2.048 mhz or 1.544 mhz) cmr1.dcs = 1: synchronized on recovered line clock
octalliu tm pef 22508 e functional description data sheet 66 rev. 1.0, 2005-06-02 figure 24 jitter attenuation performance (e1) figure 25 jitter attenuation performance (t1/j1) also the requirements of etsi tbr12/13 are satisfied. insuring adequate margin against tbr12/13 output jitter limit with 15 ui input at 20 hz the dco-r circuitry starts jitter attenuation at about 2 hz. 3.7.9.2 jitter tolerance (e1) the octalliu tm receiver?s tolerance to input jitter complies with itu for cept applications. figure 26 and figure 27 shows the curves of different input jitter specifications stated below as well as the octalliu tm performance. itd10312 1 -60 frequency attenuation 10 100 1000 10000 100000 hz itu g.736 template -50 -40 -30 -20 -10 0 10 db falc r itd10314 1 -70 frequency attenuation -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 db hz slope slope - - 40 20 db/decade db/decade falc pub 62411_h pub 62411_l r
data sheet 67 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 26 jitter tolerance (e1) figure 27 jitter tolerance (t1/j1) jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz ui 1 0.1 10 100 1000 pub 62411 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc ? f0025 jitter amplitude jitter frequency 1 10 100 1000 10000 100000 hz ui 1 0.1 10 100 1000 pub 62411 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc ? f0025
octalliu tm pef 22508 e functional description data sheet 68 rev. 1.0, 2005-06-02 3.7.9.3 output jitter in the absence of any input jitter the octalliu tm generates the intrinsic output jitter, which is specified in the table 20 below. 3.7.10 dual receive elastic buffer for jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by the clock & data recovery and are read out with the de-jittered clock sourced by dco-r, see figure 17 . if the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed. if the receive elastic buffer is read out with the receive framer clock fclkr of the framer interface (fclkr is input), the receive elastic buffer performs a clock adoption from the recovered receive clock to fclkr. the receive elastic buffer can buffer two data streams so that dual rail mode is possible at the receive framer interface (rdop/rdon). in case of single rail mode on the receive framer interface, the bipolar violation signal bpv is buffered in the same way as the single rail signal and is supported at multi function pin rdon. the size of the elastic buffer can be configured independently for the receive and transmit direction. programming of the receive buffer size is done by dic1.rbs(1:0), of the transmit buffer size by dic1.xbs(1:0) see table 21 : the functions are: clock adoption between framer receive clock (fclkr input) and internally generated route clock (recovered line clock), see chapter 3.7.9 . compensation of input wander and jitter. reporting and controlling of slips table 20 output jitter (e1) specification measurement filter bandwidth intrinsic output jitter (ui peak to peak) lower cutoff upper cutoff itu-t i.431 20 hz 100 khz < 0.015 700 hz 100 khz < 0.015 etsi tbr 12 40 hz 100 khz < 0.11 pub 62411 10 hz 8 khz < 0.015 8 hz 40 khz < 0.015 10 hz 40 khz < 0.015 broadband < 0.02 table 21 receive (transmit) elastic buffer modes dic1.rbs(1:0) (dic1.xbs(1:0)) mode frame buffer size (bits) maximum of wander (ui = 648 ns) average delay after performing a slip slip performance 00 10 e1 512 190 256 yes t1/j1 396 140 193 01 01 e1 256 100 128 t1/j1 193 74 96 10 11 (short buffer mode) e1 96 38 48 t1/j1 11 00 e1 bypass of the receive (transmit) elastic buffer no t1/j1 bypass of the receive (transmit) elastic buffer
data sheet 69 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description in ?one frame? or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or 46 bits. in bypass mode the time slot assigner is disabled. slips are performed in all buffer modes except the bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. figure 28 gives an idea of operation of the dual receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s +, s ?). if a slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rclk and the current working clock of the receive backplane interface. i.e. on the position of pointer r and w within the memory. a positive/negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 28 the receive elastic buffer as circularly organized memory 3.8 additional receiver functions 3.8.1 error monitoring and alarm handling the following error monitoring and alarm handling is supported by the octalliu tm : loss-of-signal: detection and recovery is flagged by bit lsr0.los and isr2.los. transmit line shorted: detection and release is flagged by bit lsr1.xls and isr1.xlsc transmit ones-density: detection and release is flagged by bit lsr1.xlo and isr1.xlsc limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r? s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip
octalliu tm pef 22508 e functional description data sheet 70 rev. 1.0, 2005-06-02 3.8.2 automatic modes the following automatic modes are performed by the octalliu tm : automatic clock source switching (see also: in slave mode (lim0.mas = 0) the dco-r synchronizes to the recovered route clock. in case of loss-of-signal (los) the dco-r switches to master mode automatically. if bit cmr1.dcs is set, automatic switching from the recovered route clock to sync is disabled. see also table 19 . automatic transmit clock switching, see chapter 3.9.3 . automatic local and remote loop switching based on in-band loop codes, see chapter 3.11.2 . 3.8.3 error counter the octalliu tm offers two error counters where each of them has a length of 16 bit: code violation counter, status registers cvcl and cvch prbs error counter, status registers becl and bech the error counters are buffered. buffer updating is done in two modes: one-second accumulation on demand by handshake with writing to the dec register in the one-second mode an internal/external one-second timer updates these buffers and resets the counter to accumulate the error events in the next one-second period. the error counter cannot overflow. error events occurring during an error counter reset are not lost. 3.8.4 one-second timer a one-second timer interrupt can be generated internally to indicate that the enabled alarm status bits or the error counters have to be checked. the one-second timer signal is output on port sec/fsc if configured by gpc1.csfp(1:0) ( gpc1 ). optionally synchronization to an external second timer is possible which has to be provided on pin sec/fsc. selecting the external second timer is done with gcr.ses. table 22 summary of alarm detection and release alarm detection condition clear condition loss-of-signal (los) no transitions (logical zeros) in a programmable time interval of 16 to 4096 consecutive pulse periods. programmable receive input signal threshold programmable number of ones (1 to 256) in a programmable time interval of 16 to 4096 consecutive pulse periods. a one is a signal with a level above the programmed threshold. transmit line short (xls) more than 3 pulse periods with highly increased transmit line current on xl1/2 transmit line current limiter inactive, see also chapter 3.9.7 transmit ones-density (xlo) 32 consecutive zeros in the transmit data stream on xl1/2 cleared with each transmitted pulse
data sheet 71 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description 3.9 transmit path the transmit path of the octalliu tm is shown in figure 29 . figure 29 transmit system of one channel the serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following functions: ais generation (blue alarm) generation of in-band loop-up/-down code 3.9.1 transmit line interface the principle transmit line interface is shown in figure 30 . two application modes are possible: for non-generic applications pins xl3 and xl4 can be left open. the serial resistance r ser is dependent on the operation mode (e1/t1/j1) as shown in table 23 . for generic e1/t1/j1 applications with optimized return loss the transmit output resistance is configured by using the pins xl3 and xl4 as shown in figure 30 . the operation mode (e1/t1/j1) is selected by software (register bit pc6.tsre) without the need for external hardware changes: here r ser is always 2 ? , see table 23 . in e1 mode the value of r ser in table 23 is valid for both characteristic line impedances z 0 = 120 ? and z 0 = 75 ? . shorts between xl1 and xl2 cannot be detected, see chapter 3.9.7 . the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided on pin xdi and the digital transmitter. pulse shaper, lbo encoder xdip xclk xl2 dco-x dual transmit elastic buffer mclk octalliu _its10305 tr ansmi t li ne interface e: controlled by cmr2.ixsc and cmr2.irsc f: contr ol l ed by cmr1.dxss and automati c tr ansmi t cl ock swi tchi ng g: contr ol l ed by lim1.rl,jatt and lim2.elt h: contr ol l ed by dic1.xbs( 1:0) and automati c tr ansmi t cl ock swi tchi ng %: di vi der : contr ol l ed by cmr6.stf( 2:0) master clocking unit dac xl1/xoid g h e f % fclkr tclk fclkx automatic transmit cl ock s wi tchi ng recovered receive clock internal transmit clock from dco- r (in) xl4 xl3 xdin
octalliu tm pef 22508 e functional description data sheet 72 rev. 1.0, 2005-06-02 figure 30 transmit line interface similar to the receive line interface two different data types are supported: ternary signal: single-rail data is converted into a ternary signal which is output on pins xl1 and xl2. selection between b8zs or simple ami coding is provided. unipolar data on port xoid is transmitted in cmi code with or without (dic3.cmi) preprocessed by b8zs coding or hdb3 precoding (mr3.cmi) to a fiber-optical interface. clocking off data is done with the rising edge of the transmit clock xclk (1544 khz) and with a programmable polarity. selection is done by mr0.xc1 = 0 and lim1.drs = 1. an overview of the transmit line coding is given in table 12 . 3.9.2 transmit clock tclk the transmit clock input tclk (multi function port) of the octalliu tm can be configured for 1.544, 3.088, 6.176, 12.352 and 24.704 mhz input frequency in t1/j1 mode and 2.048, 4.096, 8.192, 16.384 and 32.768 mhz input frequency in e1 mode. frequency selection is done by the register bits cmr6.stf(2:0) ( cmr6 ). see divider ?%? in figure 29 . 3.9.3 automatic transmit clock switching the transmit clock output xclk can be derived from tclk directly. in this case the tclk frequency must be 32.768 mhz in e1 or 24.704 mhz in t1/j1 mode. or with using the dco-x, were the dco-x reference is tclk. if tclk fails, the transmit clock output xclk will also fail. to avoid this, a so called automatic transmit clock switching can be enabled by setting the register bit cmr6.atcs ( cmr6 ). then fclkx will be used instead of tclk if tclk is lost. the transmit elastic buffer must be active. automatically switching between tclk and fclkx is done in the following both cases: if the tclk input is used directly as source for the transmit clock xclk, the output of the dco-x is not used. the dco-x reference clock is fclkx. if loss of tclk is detected, the transmit clock xclk will be switched automatically (if cmr6.atcs = 1) to the dco-x output which is synchronous to fclkx (see multiplexer ?h? in figure 29 ). if xclk was switched to the dco-x output and tclk becomes active, switching of xclk (back) table 23 recommended transmitter configuration values r ser (ohm), accuracy +/- 1 % application mode pc6.tsre xl3, xl4 operation mode 2 1) 1) the values in this column refers to an ideal transformer without any parasitics. any transformer resistance or other parasiti c resistances have to be taken into account when calculating the final value of the output serial resistors. generic 1 connected to r ser and xformer junction e1 2 0 t1/j1 7.5 non generic 0 left open e1 2 0 left open t1/j1 r ser r ser 1% 1% xl3 xl1 xl4 xl2 t 2 : t 1
data sheet 73 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description to tclk is automatically performed if cmr6.atcs = 1. all switchings of xclk between tclk and the dco- x output are shown in the interrupt status bit isr7.xclkss0 which is masked by imr7.xclkss0. these kinds of switching cannot be done in general without causing phase jumps in the transmit clock xclk. additionally after loss of tclk the transmit clock xclk is also lost during the ?detection time? for loss of tclk and the transmit pulses are disturbed. if cmr6.atcs is cleared, tclk is used (again) as source for the transmit clock xclk, independent if tclk is lost or not. the interrupt status bit isr7.xclkss0 will be set also. if the transmit clock xclk is sourced by the dco-x output and the dco-x reference clock is tclk, the dco- x reference will be switched automatically (if cmr6.atcs = 1) to fclkx (see multiplexer ?f? in figure 29 ) after a loss of tclk was detected. if the dco-x reference was switched to fclkx and tclk becomes active, switching of the reference (back) to tclk is automatically performed if cmr6.atcs = 1. all switchings of the reference between tclk and fclkx are shown in the interrupt status bit isr7.xclkss1 which is masked by imr7.xclkss1. for these kinds of automatically switching, the transmit clock xclk fulfills the jitter-, wander- and frequency deviation- requirements as specified for e1/t1 after the clock source of the dco-x was changed. if cmr6.atcs is cleared, tclk is used (again) as reference for the dco-x, independent if tclk is lost or not. the interrupt status bit isr7.xclkss1 will be set also. the status register bits clkstat.tclklos and clkstat.fclkxlos ( clkstat ) show if the appropriate clock is actual lost or not, so together with isr7.xclkss1 and isr7.xclkss0 the complete information regarding the current status of the transmit clock system is provided. 3.9.4 transmit jitter attenuator the transmit jitter attenuator is based on the so called dco-x (digital clock oscillator, transmit) in the transmit path. jitter attenuation of the transmit data is done in the transmit elastic buffer, see figure 29 . the dco-x circuitry generates a "jitter-free" transmit clock and meets the e1 requirements of itu-t i.431, g. 736 to 739, g.823 and etsi tbr12/13 and the t1 requirements of at&t pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr- tsy 499 and itu-t i.431, g.703 and g. 824. the dco-x circuitry works internally with the same high frequency clock as the dco-r. it synchronizes either to the working clock of the transmit system interface (internal transmit clock) or the clock provided on multi function pin tclk or the receive clock rclk (remote loop/loop-timed). the dco-x attenuates the incoming jitter starting at its corner frequency with 20 db per decade fall-off. with the jitter attenuated clock, which is directly depending on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (512/386 bit) or from the jatt buffer (512/386 bit, remote loop), see figure 31 . wander with a jitter frequency below the corner frequency is passed transparently. the dual transmit elastic buffer can buffer two data streams so that dual rail mode is possible at the transmit framer interface (xdip/xdin). the dco-x is equivalent to the dco-r so that the principle for its configuring is the same, see figure 23 and cmr3 , cmr4 and cmr5 . the dco-x reference clock is monitored: if one, two or three clock periods of the 2.048 mhz (1.544 mhz in t1/j1 mode) clock at fclkx are missing the dco-x regulates its output frequency. if four or more clock periods are missing the dco-x circuitry is automatically centered to the nominal frequency of 2.048 mhz (1.544 mhz in t1/j1) if the center function of dco-x is enabled by cmr2.dcoxc = 1. the actual dco-x output frequency is ?frozen? if the center function of dco-r is disabled by cmr2.dcoxc = 0. the jitter attenuated clock is output on pin xclk if the transmit jitter attenuator is enabled, see multiplexer ?h? in figure 29 . the transmit jitter attenuator can be disabled. in that case data is read from the transmit elastic buffer with the clock sourced on pin tclk, see multiplexer ?h? in figure 29 . synchronization between fclkx and tclk has to be done externally. in the loop-timed clock configuration (lim2.elt) the dco-x circuitry generates a transmit clock which is frequency synchronized on rclk, see figure 31 and multiplexers ?g? and ?f? in figure 29 . in this configuration the transmit elastic buffer has to be enabled.
octalliu tm pef 22508 e functional description data sheet 74 rev. 1.0, 2005-06-02 figure 31 clocking and data in remote loop configuration 3.9.5 dual transmit elastic buffer the received single rail bit stream from pin xdi or dual rail bit stream from the pins xdip and xdin are optionally stored in the transmit elastic buffer, see figure 29 . the tansmit elastic buffer is organized as the receive elastic buffer. the functions are also equal to the receive side. programming of the dual transmit buffer size is done by dic1.xbs(1:0) in the same way as programming of the dual receive buffer size by dic1.rbs(1:0), see table 21 : the functions of the transmit buffer are: clock adoption between framer transmit clock (fclkx) and internally generated transmit route clock, see chapter 3.9.4 . compensation of input wander and jitter. reporting and controlling of slips writing of received data from xdip/xdin is controlled by the internal transmit clock. selection of fclkx or fclkr is possible, see multiplexer ?e? in figure 29 . (if the dco-r output is selected, the dco_r output is also output at fclkr.) reading of stored data is controlled by the clock generated either by the dco-x circuitry or the externally generated tclk. with the de-jittered clock data is read from the dual transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is done according to the receive direction. positive/negative slips are reported in interrupt status bits isr4.xsp and isr4.xsn. if the transmit buffer is bypassed data is directly transferred to the transmitter. 3.9.6 programmable pulse shaper and line build-out the transmitter includes a programmable pulse shaper to generate transmit pulse masks according to: for t1: fcc68; ansi t1. 403 1999, figure 4; itu-t g703 11/2001, figure 10 (for different cable lengths), see figure 56 and figure 33 for measurement configuration were r load = 100 ? for e1: itu-t g703 11/2001, figure 15 (for 0 m cable length) see figure 55 ; itu-t g703 11/2001, figure 20 (for dcim mode), see figure 32 for measurement configuration were r load = 120 ? or r load = 75 ? the transmit pulse shape (u pulse ) is programmed either pulse shaper, lbo encoder xdata xclk xl2 dco-x mclk octalliu _rem ote_loop_clocking tr ansmit li ne interface master clocking unit dac xl1/xoid1 g h e f % fclkr tclk fclkx recovered receive clock equalizer cl ock & data recovery decoder rl1/roid rl2 recei ve li ne interface dpll ja tt buffer rdata automatic transmit cl ock s wi tchi ng from dco-r xl4 xl3
data sheet 75 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description by the registers xmp(2:0) compatible to the quadliu tm , see table 24 and table 25 , if the register bit xpm2.xpdis is cleared, see xpm2 or by the registers txp(16:1), see txp1 , if the register bit xpm2.xpdis is set, see table 26 and table 27 . for more details see chapter ?operational description? to reduce the crosstalk on the received signals in long haul applications the octalliu tm offers the ability to place a transmit attenuator (line build-out, lbo) in the data path. this is used only in t1 mode. lbo attenuation is selectable with the values 0, -7.5, -15 or -22.5 db (register bits lim2 .lbo(2:1)). ansi t1. 403 defines only 0 to - 15 db. figure 32 measurement configuration for e1 transmit pulse template figure 33 measurement configuration for t1/j1 transmit pulse template 3.9.6.1 quadliu tm compatible programming after reset xpm2.xpdis is zero so that programming with xpm(2:0) is selected. the default setting after reset for the registers xmp(2:0) generates the e1 pulse shape, see table 25 , but with an unreduced amplitude. no reset value for t1 mode exists. so after switching into t1 mode, an explicit new programming like described in table 24 is necessary. if lbo attenuation is selected, the programming of xpm(2:0) will be ignored. instead the pulse shape programming is handled internally: the generated pulse shape before lbo filtering is the same as for t1 0 to 40 m. the given values are optimized for transformer ratio: 1 : 2.4 and cable type awg24 using transmitter configurations listed in table 23 and shown in figure 30 . the measurement configurations of figure 32 with r load = 120 ? and figure 33 with r load = 100 ? are used. table 24 recommended pulse shaper programming for t1/j 1 with registers xpm(2:0) (compatible to quadliu ) lbo range range xpm0 xpm1 xpm2 (db) (m) (ft) hexadecimal 0 0 to 40 0 to 133 d7 22 11 0 40 to 81 133 to 266 fa 26 11 0 81 to 122 266 to 399 3d 37 11 oct alli u_pulse_meas_t emp_e1 octalliu tm r ser r load u pu l se see chapt er 3. 6. 1. xl1 xl2 xl3 xl4 oct alli u_pulse_meas_t emp_t1 octal liu tm r ser cabl e, z 0 r load 0 t o 200 m u pu lse see chapt er 3. 6. 1. xl1 xl2 xl3 xl4 (0 t o 655 f t )
octalliu tm pef 22508 e functional description data sheet 76 rev. 1.0, 2005-06-02 3.9.6.2 programming with txp(16:1) registers by setting of register bit xpm2.xpdis the pulse shape will be configured by the registers txp(16:1) ( txp1 ). every of these registers define the amplitude value of one sampling point in the symbol. a symbol is formed by 16 sampling points. the default setting after reset for the registers txp(16:1) generates also the e1 pulse shape (0m), but with an unreduced amplitude. (txp(9:16) = 00 h ; txp(1:8) = 38 h = 56 d ) no reset value for t1 mode exists. so after switching into t1 mode, an explicit new programming like table 26 is necessary. the pulse shape configuration will be done also by the registers txp(16:1) if a lbo attenuation is selected. the pulse shape is then determined by both, the values of txp(16:1) and the lbo filtering. the given values in table 26 and table 27 are optimized for transformer ratio: 1 : 2.4; cable: awg24 and configurations listed in table 23 and shown in figure 30 . 0 122 to 162 399 to 533 5f 3f 11 0 162 to 200 533 to 655 3f cb 11 7.5 --- are not taken into account: pulse shape generation is handled internally. 15 --- 22.5 --- table 25 recommended pulse shaper programming for e1 with registers xpm(2:0) (compatible to octalliu tm ) r ser z 0 transmit line interface mode xpm0 xpm1 xpm2 (? ) ( ? ) hexadecimal 7.5 1) 1) the values in this row refers to an ideal application without any parasitics. any other parasitic resistances have to be take n into account when calculating the final value of the output serial resistors. 120 non generic 9c 03 00 7.5 75 non generic 8d 03 00 --- reset values 7b 03 40 7.5 dcim mode non generic ef bd 07 table 26 recommended pulse shaper programming for t1 with registers txp(16:1) lbo range range txp values, decimal [db] [m] [ft] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 to 40 0 to 133 46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4 0 40 to 81 133 to 266 48 50 48 46 46 44 44 44 16 -17 -14 -14 -4 -4 -4 -4 0 81 to 122 266 to 399 56 58 54 52 48 48 48 48 16 -25 -17 -14 -4 -4 -4 -4 0 122 to 162 399 to 533 63 63 58 56 52 52 51 51 16 -34 -32 -17 -4 -4 -4 -4 0 162 to 200 533 to 655 63 63 63 58 50 50 50 50 50 -60 -26 -20 -12 -8 -6 -4 7.5 -- -- 46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4 155 -- -- 46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4 22.5 -- -- 46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4 table 24 recommended pulse shaper programming for t1/j1 with registers xpm(2:0) (compatible to quadliu (cont?d) ) lbo range range xpm0 xpm1 xpm2
data sheet 77 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description 3.9.7 transmit line monitor the transmit line monitor (see principle in figure 34 ) compares the transmit line current on xl1 and xl2 with an on-chip transmit line current limiter. the monitor detects faults on the primary side of the transformer indicated by a highly increased transmit line current (more than 120 ma for at least 3 consecutive pulses sourced by vddx) and protects the device from damage by setting the transmit line driver xl1/2 into high-impedance state automatically (if enabled by xpm2.daxlt = 0, see xpm2 ). the current limiter checks the actual current value of xl1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared. two conditions are detected by the monitor: transmit line ones density (more than 31 consecutive zeros) indicated by lsr1.xlo ( lsr1 ). transmit line high current indicated by lsr1.xls. in both cases a transmit line monitor status change interrupt is provided. shorts between xl1 or xl2 and v dd , v ddc or v ddp are not detected. note that shorts between xl1 and xl2 were not detected. this way a short between xl1 and xl2 will not ham the device. figure 34 transmit line monitor configuration table 27 recommended pulse shaper programming for e1 with registers txp(16:1) r ser z 0 transmit line interface mode txp values, decimal ( ? ) ( ? ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1) 1) the values in this row refers to an ideal application without any parasitics. any other parasitic resistances have to be take n into account when calculating the final value of the output serial resistors. 120 generic 42 40 40 40 40 40 40 42 0 0 0 0 0 0 0 0 7.5 120 non generic 63 57 57 57 57 57 57 57 -4 0 0 0 0 0 0 0 2 75 generic 42 40 40 40 40 40 40 40 0 0 0 0 0 0 0 0 7.5 75 non generic 60 58 58 58 58 58 58 58 0 0 0 0 0 0 0 0 -- reset values 56 56 56 56 56 56 56 56 0 0 0 0 0 0 0 0 2 dcim mode generic 20 20 20 20 20 20 20 20 -20 -20 -20 -20 -20 -20 -20 -20 7.5 dcim mode non generic 28 28 28 28 28 28 28 28 -28 -28 -28 -28 -28 -28 -28 -28 its10936 pulse shaper monitor line tri xdata xl1 xl2
octalliu tm pef 22508 e functional description data sheet 78 rev. 1.0, 2005-06-02 3.10 framer interface the framer interface of the octalliu tm is shown in figure 35 . figure 35 framer interface (shown for one channel) configuring of the framer interface consists on configuration of the interface mode (single/dual rail) configuration of the multi function ports, see chapter 3.12 selection of dual or single rail mode can be done in receive and transmit direction independent from each other. in single rail mode of the receive direction (lim3.drr = 0, lim3 ), the unipolar data is supported at rdop and the bipolar violation (bpv) is supported at the receive multifunction pins. therefore one of the three receive multifunction pins must be configured to rdon/bpv output (for example pc3.rpx3(3:0) = 1110 b ), see table 29 , if bpv output is used exernally. if dual rail mode is selected in receive direction by setting of register bit lim3.drr, the positive rail of the data is supported at rdop and the negative rail of the data or is supported at the receive multi function pins. therefore one of the three receive multifunction pins must be configured to rdon/bpv output, see table 29 . clocking of rdop and rdon/bpv is done with the rising or falling edge of the internal receive clock, selected by dic3.resr. the internal receive clock can be sourced either by the receive clock rclk of the receive system (cmr2.irsc = 1, cmr2 ). to support the framer with these clock fclkr output pin function must be selected by pc5.csrp = 1 ( pc5 ). or receive framer interface transmit framer interface transmit system (see chapter 3.8.) fclkr rp(a...c) fclkx xp(a...b) xdip tclk tclk xclk receive system (see chapter 3.6) fclkx internal transmit cl ock dual transmit eastic buffer rclk dual receive elastic buffer los rdon/bpv rclk xdin multi function ports multi function ports octalliu_framer_if internal receive clock k j: controlled by cmr2.irsc and dic1.rbs(1:0) k: controlled by cmr2.ixsc 1: input/output selection of fclkr by pc5.csrp rdon/bpv los rdop rdop j xdin xdip recovered cl ock from dco-r 1
data sheet 79 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description by the fclkr input pin. in that case fclkr input pin function must be selected by pc5.csrp = 0 to use the receiver clock from the framer. in single rail mode of the transmit direction (lim3.drx = 0, lim3 ), the input for the unipolar data of the framer is xdip. if dual rail mode is selected in transmit direction by setting of register bit lim3.drx, the input for the positive rail of the data is xdip and the input for the negative rail of the data is the multi function port xdin. therefore one of the both transmit multifunction ports must be configured to xdin (for example pc1.xpx1(3:0) = 1101 b ), see table 29 . clocking (sampling) of xdip and xdin is done with the rising or falling edge of the internal transmit clock, selected by dic3.resx. the internal transmit clock can be sourced either by the internal receive clock of the receive system (cmr2.ixsc = 1). to support the framer with these clock fclkr output pin function must be selected by pc5.csrp = 1. or by the fclkx input pin (cmr2.ixsc = 0). in that case fclkx is supported by the framer. 3.11 test functions the following chapters describe the different test function of the octalliu tm . 3.11.1 pseudo-random binary sequence ge neration and monitor all bits of all slots in a e1t1/j1 frame are used for prbs. the octalliu tm has the ability to generate and monitor pseudo-random binary sequences (prbs). the generated prbs pattern is transmitted to the remote end on pins xl1/2 and can be inverted optionally. generating and monitoring of prbs pattern is done according to itu-t o.150 and itu-t o.151. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non-inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error increments an error counter bec ( becl ). synchronization is reached within 400 ms with a probability of 99.9% at a bit error rate of up to 10 -1 . the prbs pattern (polynomials) can be selected to be 211-1, 215-1, 220-1or 223-1 by the register bits tpc0.prp(1:0) and lcr1.llbp ( lcr1 ), see table 28 . for definition of this polynomials see the standards itu-t o.150, o.151. and tr62441. the polynomials 211-1 and 223-1 can be selected only if tpc0.prm unequal 00 b . transmission of prbs pattern is enabled by register bit lcr1.xprbs. with the register bit lcr1.fllb switching between not inverted and inverted transmit pattern can be done. the receive monitoring of prbs patterns is enabled by register bit lcr1.eprm. in general, depending on bit lcr1.eprm the source of the interrupt status bit isr1.llbsc changed, see register description. the type of detected prbs pattern in the receiver is shown in the status register bits prbssta.prs. every change of the bits prs in prbssta sets the interrupt bit isr1.llbsc if register bit lcr1.eprm is set. no pattern is also detected if the mode ?alarm simulation? is active. the detection of all_zero or all_ones pattern is done over 12, 16, 21 or 24 consecutive bits, depending on the selected prbs polynomial (211-1, 215-1, 220-1or 223-1 respectively). the detection of all_zero or all_ones is independent on lcr1.fllb. the distinction between all-ones and all-zeros pattern is possible by combination of. the information about the first reached prbs status after the prbs monitor was enabled (?prbs pattern detected? or ?inverted prbs pattern detected?) with the status information ?all-zero pattern detected? or ?all-ones pattern detected? if an ?all-one? or an ?all-zero? pattern is detected by the prbs monitor, the interrupt status bit isr1.llbsc in e1 mode, or isr3.llbsc in t1/j1 mode respectively, is set not only once, but is set permanent. therefore, after reading of the interrupt status bit isr1.llbsc (e1 mode) or isr3.llbsc (t1/j1 mode), the appropriate interrupt routine should set the interrupt mask bits imr1.llbsc (e1 mode) or imr3.llbsc (t1/j1 mode) to 1, after an ?all-one? or an ?all-zero? pattern was indicated, to avoid permanent interrupts issued by the octalliu tm . the prbs status register bits prbssta.prs should be polled to detect changes in the pattern, for
octalliu tm pef 22508 e functional description data sheet 80 rev. 1.0, 2005-06-02 example once per second, using the isr3.sec interrupt. in case prbssta.prs(2:1) is unequal 11 b , the interrupt mask bits should be cleared to return to normal operation. because every bit error in the prbs sequence increments the bit error counter bec, no special status information like ?prbs detected with errors? is given here. 3.11.2 in-band loop generation, detection and loop switching detection and generation of in-band loop code is supported by the octalliu tm on the line side and on the framer side independent from another. the octalliu tm generates and detects unframed in-band codes where the complete data stream is used by the in-band signaling information.the so called loop-up code (for loop activation) and loop-down code (for loop deactivation) are recognized. the maximum allowed bit error rate within the loop codes can be up to 10 -2 for proper detection of the loop codes. one ?in-band loop sequence? consists of a bit sequence of 51200 consecutive bits. the in-band loop code detection is based on the examination of such ?in-band loop sequences?. the following in-band loop code functionality is performed by the octalliu tm : the necessary reception time of in-band loop codes until an automatic loop switching is performed is configured for the system side by the register bits inbldtr.inbldt(1:0) ( inbldtr ). configuring for the line side is done by inbldtr.inbldr(1:0). if for example inbldtr.inbldr(1:0) = 00 b a time of 16 ?in-band loop sequences? (16 x 51200 bits) is selected for the line side. the interrupt status register bits isr6.(3:0) reflects the type of detected in-band loop code. masking can be done by imr6(3:0). the status bits are set after one ?in-band loop sequence? is detected (no dependency on inbldtr). transmission of in-band loop codes is enabled by programming mr3.xld/xlu in e1 mode or mr5.xld/xlu in t1/j1 mode. transmission of codes is done by the octalliu tm lasting for at least 5 seconds. the octalliu tm also offers the ability to generate and detect flexible in-band loop-up and loop-down patterns (lcr1.llbp = 1) ( lcr1 ). programming of these patterns is done in registers lcr2 and lcr3 ( lcr2 ). the pattern length is individually programmable in length from 2 to 8 bits by lcr1.lac(1:0) and lcr1.ldc(1:0). a shorter pattern can be inplemented by configuring a repeating pattern in the lcr2 and lcr3. automatic loop switching (activation and deactivation, for remote loop, see chapter 3.11.3 and local loop, see chapter 3.11.4 ) based on in-band loop codes can be done. two kinds of line loop back (llb) codes are defined in ansi-t1.403, 1999 in chapter 9.4.1.1 and 9.4.1.2. respectively. automatic loop switching must be enabled through configuration register bits als.sils for the in-band loop codes coming from the system side and als.lils for the in-band loop codes coming from the line side respectively. masking of isr6.(3:0) for interrupt can be done by register bits imr6.(3:0). the interrupt status register bits isr6.(3:0) ( isr6 ) will be set to 1 if an appropriate in-band code were detected, independent if automatic loop switching is enabled. (because the controller knows if automatic loop switching is enabled, it knows if a loop is activated or not.) code detection status only for the line side is displayed in e1 mode in status register bits lsr2.llbdd / llbad and in t1/j1 mode in lsr1.llbdd / llbad. only unframed in-band loop code can be generated and detected. automatic loop switching is logically ord with the appropriate loop switching by register bits. table 28 supported prbs polynomials tpc0.prp(1:0) tpc0.prm lcr1.llbp kind of polynomial comment 00 01 or 11 x 2 11 -1 01 01 or 11 x 2 15 -1 10 01 or 11 x 2 20 -1 11 01 or 11 x 2 23 -1 xx 00 0 2 15 -1 sw compatible to quadliu xx 00 1 2 20 -1
data sheet 81 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description if a remote loop is activated by an automatic loop switching the register bit lim0.jatt controls also if the jitter attenuator is active or not, see also figure 31 . if als.lils is set ( als ), the remote loop is activated after an activation in-band loop code (see ansi t1 404, chapter 9.4.1.1.) was detected from the line side and if the local loop is not activated by lim0.ll = 1. the remote loop is deactivated after a deactivation in-band loop code (see ansi t1 404, chapter 9.4.1.2.) was detected from the line side. (but if the remote loop is additionally activated by lim0.rl = 1 the remote loop is still active, because automatic loop switching is logically ord with the appropriate loop switching by register bits.). if als.sils is set, the local loop is activated after an activation in-band loop code (see ansi t1 404, chapter 9.4.1.1.) was detected from the system side. the local loop is deactivated after a deactivation in-band loop code (see ansi t1 404, chapter 9.4.1.2.) was detected from the system side. (but if the local loop is additionally activated by lim0.ll = 1 the local loop is still active, because automatic loop switching is logically ord with the appropriate loop switching by register bits.). als.sils and als.lils both must not be set to 1 simultaneous. if als.sils or als.lils are set after an in-band loop code was detected, no automatic loop switching is performed. if als.lils is cleared, an automatic activated remote loop is deactivated. if als.sils is cleared, an automatic activated local loop is deactivated. the kind of detected in-band loop codes is shown in the interrupt status register bits isr6.(3:0). to avoid deadlocks in the octalliu tm an activation of the remote loop is not possible by in-band loop codes if the local loop (see chapter 3.11.4 ) is closed (lim0.ll is set). 3.11.3 remote loop in the remote loop-back mode the clock and data recovered from the line inputs rl1/2 or roid are routed back to the line outputs xl1/2 or xoid through the analog or digital transmitter, see figure 36 and figure 31 . as in normal mode they are also sent to the framer interface. the remote loop-back mode is activated by control bit lim1.rl or after detection of the appropriate in-band loop code, if enabled by als.lils and if lim0.ll = 0 ( lim0 ) (to avoid deadlocks), see chapter 3.11.2 . received data can be looped with or without the jitter attenuator (jatt buffer) dependent on lim1.jatt ( lim1 ). figure 36 remote loop pulse shaper, lbo encoder xdata xl2 octal liu _rem ote_loop tr ansmi t li ne interface dac xl1/xoid equalizer cl ock & data recovery decoder rl1/roid recei ve line interface dpll ja tt buffer rdata clocking rl2
octalliu tm pef 22508 e functional description data sheet 82 rev. 1.0, 2005-06-02 3.11.4 local loop the local loop-back is activated by the control bit lim0.ll ( lim0 ). after detection of the appropriate in-band loop code, if enabled by als.sils, see chapter 3.11.2 . the local loop-back mode disconnects the receive lines rl1/2 or roid from the receiver. instead of the signals coming from the line the data provided by the framer interface is routed through the analog receiver back to the framer interface. however, the bit stream is transmitted undisturbed on the line at xl1/2. however, an ais to the distant end can be enabled by setting mr1.xais = 1 without influencing the data looped back to the framer interface. the signal codes for transmitter and receiver have to be identical. figure 37 local loop 3.11.5 payload loop-back the payload loop-back is activated by setting mr2.plb ( mr2 ). during activated payload loop-back the data stream is looped from the receiver section back to transmitter section. the looped data passes the complete receiver including the wander and jitter compensation in the receive elastic buffer and is output on pin rdo. instead of the data an ais signal (mr2.sais) can be sent to the framer interface. if the plb is enabled the transmitter and the data on pins xl1/2 or xdop/xdon are clocked with fclkr instead of fclkx. all the received data is processed normally. octalliu _local_loop equalizer cl ock & data recovery decoder rdop rclk rl1/roid rl2 dco-r dual receive elastic buffer recei ve li ne interface dpll a d j int ernal receive clock rdon c pulse shaper, lbo encoder xdip xl2 dco-x dual transmit elastic buffer tr ansmi t line interface dac xl1 g h e f % tclk fclkx recovered receive clock int ernal transmit clock xl4 xl3 xdin local loop
data sheet 83 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e functional description figure 38 payload loop 3.11.6 alarm simulation alarm simulation does not affect the normal operation of the device. however, possible real alarm conditions are not reported to the micro controller or to the remote end when the device is in the alarm simulation mode. the alarm simulation and setting of the appropriate status bists is initiated by setting the bit mr0.sim. for details (differences between e1 and t1/j1 mode) see description in mr0 . the following alarms are simulated: loss-of-signal (los) alarm indication signal (ais) code violation counter (hdb3 code) error counting and indication occurs while this bit is set. after it is reset all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. alarms like ais and los are cleared automatically. interrupt status registers and error counters are automatically cleared on read. 3.12 multi function ports several signals are available on the multi function ports, see table 29 and pc1 . after reset, input function is selected (0000 b ) with exception of the ports rpc were rclk output is selected: the register bits pc3.rpc2 have the reset value fh. (note that pc5.crp must be set to 1 for an active rclk output. after reset pc5.crp is 0 and rclk is pulled up.) three multi function ports (mfp) for rx - so called as rpa, rpb, rpc - and two mfps for tx - so called as xpa, xpb - are implemented for every channel. the port levels are reflected in the appropriate bits of the register mfpi, see mfpi . the functions of rpa, rpb and rpc are configured by pc1.rpc1(3:0) , pc2.rpc2(3:0) and pc3.rpc3(3:0) respectively.the functions of xpa and xpb are configured by pc1.xpc1(3:0) and pc2.xpc2(3:0) respectively. the actual logical state of the 5 multifunction ports can be read out using the register mfpi. this function together with static output signal options in table 29 offers general purpose i/o functionality on unused multi function port pins. rclk rl1/roid rl2 dco-r recei ve li ne interface a d c payl oad loop j int ernal receive clock equalizer cl ock & data recovery decoder rdop dual receive elastic buffer dpll rdon fclkr octalliu _payload_loop pulse shaper, lbo encoder xdip xl2 dco-x dual transmit elastic buffer tr ansmi t line interface dac xl1 g h e f % tclk fclkx recovered receive clock int ernal transmit clock xl4 xl3 xdin
octalliu tm pef 22508 e functional description data sheet 84 rev. 1.0, 2005-06-02 if a port is configured as gpoh or gpol the port level is set fix to high or low-level respectively. each of the input functions may only be selected once in a channel except for the gpi functionality. no input function must be selected twice or more. if rlt is selected, it should be assigned to rpc. table 29 multi function port selection selection rfp signal available on port rfp function xfp signal available on port xfp function 0000 reserved a, b, c reserved reserved a, b reserved 0001 reserved a, b, c reserved reserved a, b reserved 0010 reserved a, b, c reserved reserved a, b reserved 0011 reserved a, b, c reserved tclk a, b transmit clock input 0100 reserved a, b, c reserved reserved a, b reserved 0101 reserved a, b, c reserved reserved a, b reserved 0110 reserved a, b, c reserved reserved a, b reserved 0111 reserved a, b, c reserved xclk a, b transmit clock output 1000 rlt a, b, c receive line termination; logically ord with lim0.rtrs xlt a, b transmit line tristate control, high active 1001 gpi a, b, c general purpose input gpi a, b general purpose input 1010 gpoh a, b, c general purpose output high gpoh a, b general purpose output high 1011 gpol a, b, c general purpose output low gpol a, b general purpose output low 1100 los a, b, c loss of signal indication output reserved a, b reserved 1101 rtdmt a, b, c receive framer interface tristate for pins rdop and rclk; logically ord with dic3.rrtri xdin a, b transmit data negative input 1110 rdon a, b, c receive data negative output or bipolar violation output xlt a, b transmit line tristate control, low active 1111 rclk a, b, c rclk output reserved a, b reserved
data sheet 85 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionnotes 4 register description to maintain easy readability this chapter is divided into separate control register and status register sections. the higher address part of all global registers is 00 h , that of the port (channel) specific ones include the channel number 0 to 7 and is marked in the following tables with xx h . so xx h has the values 00 h up to 07 h . notes 1. ?res? in the register schematics means reserved, not reset. if these bits are written then the value must be 0. 2. in all bit fields used in the register schematics and also in the table descriptions the most significant bit is the left one and the least significant bit is the right one. sometimes in the text a bit field with the name ?bitfieldname? is denoted as (msb:lsb). for example: in register gpc2 the bit fiield fss consists on mds(2:0).
octalliu tm pef 22508 e register descriptionnotes data sheet 86 rev. 1.0, 2005-06-02 4.1 detailed register description table 30 registers address space module base address end address note channel xx xx00 h xxff h xx = 00h ... 07h table 31 registers overview register short name register long name offset address page number cmdr command register xx02 h 90 imr1 interrupt mask register 1 xx15 h 91 mr0 mode register 0 xx1c h 93 mr1 mode register 1 xx1d h 95 mr2 mode register 2 xx1e h 95 loop loop-back register xx1f h 96 mr4 mode register 4 xx20 h 97 mr5 framer mode register 5 xx21 h 97 rc0 receive control 0 xx24 h 98 xpm0 transmit pulse mask0 xx26 h 99 xpm1 transmit pulse mask1 xx27 h 100 xpm2 transmit pulse mask2 xx28 h 100 ccb1 clear channel register 1 xx2f h 101 mr3 mode register 3 xx31 h 102 lim0 line interface mode 0 xx36 h 103 lim1 line interface mode 1 xx37 h 105 pcd pulse count detection register xx38 h 106 pcr pulse count recovery xx39 h 106 lim2 line interface mode 2 xx3a h 107 lcr1 loop code register 1 xx3b h 108 lcr2 loop code register 2 xx3c h 110 dic1 digital interface control 1 xx3e h 111 dic2 digital interface control 2 xx3f h 112 dic3 digital interface control 3 xx40 h 112 cmr4 clock mode register 4 xx41 h 114 cmr5 clock mode register 5 xx42 h 115 cmr6 clock mode register 6 xx43 h 116 cmr1 clock mode register 1 xx44 h 117 cmr2 clock mode register 2 xx45 h 118 cmr3 clock mode register 3 xx48 h 121 pc1 port configuration 1 xx80 h 121 pc5 port configuration 5 xx84 h 124 pc6 port configuration 6 xx86 h 125 tpc0 test pattern control register 0 xxa8 h 134
data sheet 87 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionnotes txp1 tx pulse template register 1 xxc1 h 134 als automatic loop switching register xxd9 h 139 imr7 interrupt mask register 7 xxdf h 139 lim3 liu mode register 3 xxe2 h 140 rbd receive buffer delay xx49 h 140 res receive equalizer status xx4b h 141 lsr0 line status register 0 xx4c h 142 lsr1 line status register 1 xx4d h 143 lsr3 line status register 3 xx4e h 144 lsr2 line status register 2 xx4f h 146 cvcl code violation counter lower byte xx52 h 147 cvch code violation counter higher byte xx53 h 148 becl prbs bit error counter lower bytes xx58 h 149 bech prbs bit error counter higher bytes xx59 h 150 isr1 interrupt status register 1 xx69 h 151 isr2 interrupt status register 2 xx6a h 152 isr3 interrupt status register 3 xx6b h 152 isr4 interrupt status register 4 xx6c h 153 gis global interrupt status register xx6e h 154 mfpi multi function port input register xxab h 156 isr6 interrupt status register 6 xxac h 157 isr7 interrupt status register 7 xxd8 h 158 prbssta prbs status register xxda h 159 clkstat clock status register xxfe h 160 imr2 interrupt mask register 2 xx16 h 92 imr3 interrupt mask register 3 xx17 h 92 imr4 interrupt mask register 4 xx18 h 92 imr6 interrupt mask register 6 xx1a h 92 imr7 interrupt mask register 7 xxdf h 92 pc2 port configuration register 2 xx81 h 123 pc3 port configuration register 3 xx82 h 123 txp2 tx pulse template register 2 xxc2 h 135 txp3 tx pulse template register 3 xxc3 h 135 txp4 tx pulse template register 4 xxc4 h 135 txp5 tx pulse template register 5 xxc5 h 135 txp6 tx pulse template register 6 xxc6 h 135 txp7 tx pulse template register 7 xxc7 h 135 txp8 tx pulse template register 8 xxc8 h 135 txp9 tx pulse template register 9 xxc9 h 135 txp10 tx pulse template register 10 xxca h 135 txp11 tx pulse template register 11 xxcb h 135 table 31 registers overview (cont?d) register short name register long name offset address page number
octalliu tm pef 22508 e register descriptionnotes data sheet 88 rev. 1.0, 2005-06-02 the register is addressed wordwise. txp12 tx pulse template register 12 xxcc h 135 txp13 tx pulse template register 13 xxcd h 135 txp14 tx pulse template register 14 xxce h 135 txp15 tx pulse template register 15 xxcf h 135 txp16 tx pulse template register 16 xxd0 h 135 ipc interrupt port configuration 0008 h 90 ccb2 clear channel register 2 30 h 102 ccb3 clear channel register 3 31 h 102 lcr3 loop code register 3 3d h 110 gcr global configuration register 0046 h 120 vstr version status register 004a h 141 cis channel interrupt status register 006f h 155 gpc1 global port configuration 1 0085 h 125 gpc2 global port configuration register 2 008a h 126 gcm1 global clock mode register 1 0092 h 127 gcm2 global clock mode register 2 0093 h 127 gcm3 global clock mode register 3 0094 h 129 gcm4 global clock mode register 4 0095 h 129 gcm5 global clock mode register 5 0096 h 130 gcm6 global clock mode register 6 0097 h 131 gcm7 global clock mode register 7 0098 h 132 gcm8 global clock mode register 7 0099 h 133 gimr global interrupt mask register 00a7 h 133 gis2 global interrupt status 2 00ad h 157 gpc3 global port configuration register 3 00d3 h 135 gpc4 global port configuration register 4 00d4 h 136 gpc5 global port configuration register 5 00d5 h 137 gpc6 global port configuration register 6 00d6 h 138 inbldtr in-band loop detection time register 00d7 h 138 table 31 registers overview (cont?d) register short name register long name offset address page number
data sheet 89 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionnotes table 32 registers access types mode symbol description hardware (hw) description software (sw) basic access types read/write rw register is used as input for the hw register is read and writable by sw read/write virtual rwv physically, there is no new register in the generated register file. the real readable and writable register resides in the attached hardware. register is read and writable by sw (same as rw type register) read r register is written by hw (register between input and output -> one cycle delay) value written by sw is ignored by hw; that is, sw may write any value to this field without affecting hw behavior read only ro same as r type register same as r type register read virtual rv physically, there is no new register in the generated register file. the real readable register resides in the attached hardware. value written by sw is ignored by hw; that is, sw may write any value to this field without affecting hw behavior (same as r type register) write w register is written by software and affects hardware behavior with every write by software. register is writable by sw. when read, the register does not return the value that has been written previously, but some constant value instead. write virtual wv physically, there is no new register in the generated register file. the real writable register resides in the attached hardware. register is writable by sw (same as w type register) read/write hardware affected rwh register can be modified by hardware and software at the same time. a priority scheme decides, how the value changes with simultaneous writes by hardware and software. register can be modified by hw and sw, but the priority sw versus hw has to be specified. sw can read the register.
octalliu tm pef 22508 e register descriptioncommand register data sheet 90 rev. 1.0, 2005-06-02 4.1.1 control registers command register interrupt port configuration see chapter 3.5.3 and table 9 . cmdr offset reset value command register xx02 h 00 h field bits type description rres 6 w receiver reset the receive line interface except the clock and data recovery unit (dpll) is reset. however the contents of the control registers is not deleted. a receiver reset should be made after switching from power down to power up (gcr.pd = 1 -> 0). xres 4 w transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper are reset. however the contents of the control registers is not deleted. ipc offset reset value interrupt port configuration 0008 h 00 h field bits type description vispll 7 rw masked pll interrupts visible see also chapter 3.5.3 0 b , masked interrupt status bits plllc and pllic are not visible in register gis2. 1 b , masked interrupt status bits plllc and pllic are visible in gis2, but they are not visible in registers gis. 5hv z 55(6 5hv z ;5(6 5hv uz 9,63// 5hv uz 66<) uz ,&
data sheet 91 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptioninterrupt mask register 1 interrupt mask register 1 each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined by register ipc). a ?1? in a bit position of imr(1:4), imr(6:7) sets the mask active for the interrupt status in isr(1:4), isr(6:7). masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they are- not displayed in the interrupt status register if bit gcr.vis is cleared- displayed in the interrupt status register if bit gcr.vis is set, see chapter 3.5.3 . ssyf 2 rw select sync frequency only applicable in master mode (lim0.mas = 1) and bit cmr2.dcf is cleared, see also table 9. 0 b , reference clock on port sync is 2.048 mhz 1 b , reference clock on port sync is 8 khz ic 1:0 rw interrupt port configuration these bits define the function of the interrupt output pin int. x0 b , open drain output 01 b , push/pull output, active low 11 b , push/pull output, active high imr1 offset reset value interrupt mask register 1 xx15 h ff h field bits type description llbsc 7 rw interrupt mask bit llbsc each interrupt source can generate an interrupt signal on port int. characteristics of the output stage are defined by register ipc. a 1 in a bit position of imr(7:0) sets the mask active for the interrupt status in the registers isr. mask interrupt statuses neither generate a signal on int, not are they visible in register gis. moreover they are not displayed in the interrupt status register if bit gcr.vis is cleared; they are displayed in the interrupt status register if bit gcr.vis is set. the bit imr1.llbsc is only valid in e1 mode. for t1/j1 mode the equivalent bit is in imr3.llbsc. xlsc 1 rw interrupt mask bit xlsc field bits type description uz //%6& 5hv uz ;/6& 5hv
octalliu tm pef 22508 e register descriptionsimilar registers data sheet 92 rev. 1.0, 2005-06-02 similar registers the other interrupt mask registers have the same description. the offset addresses are listed in imrn overview , for bit names and layout refer to interrupt mask registers . table 33 imrn overview register short name register long name offset address page number imr2 interrupt mask register 2 xx16 h imr3 interrupt mask register 3 xx17 h imr4 interrupt mask register 4 xx18 h imr6 interrupt mask register 6 xx1a h imr7 interrupt mask register 7 xxdf h table 34 interrupt mask registers bit number 7 6 5 4 3 2 1 0 imr1 llbsc (e1 only) xlsc imr2 ais los imr3 sec llbsc (t1/j1 only) ltc rsn rsp imr4 xsp xsn imr6 lilsu lilsd imr7 xclkss1 xclkss0
data sheet 93 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionmode register 0 mode register 0 mr0 offset reset value mode register 0 xx1c h 00 h field bits type description xc 7:6 rw transmit code serial line code for the transmitter, independent of the receiver. after changing xc(1:0), a transmitter software reset is required (cmdr.xres = 1). see chapter 3.9.1 . 00 b , reserved 01 b , cmi (1t2b+hdb3), (optical interface) 10 b , ami (ternary or digital dual-rail interface) 11 b , hdb3 code in e1 or b8zs code in t1/j1 mode (ternary or digital dual-rail interface) rc 5:4 rw receive code serial line code for the receiver, independent of the transmitter. after changing rc(1:0), a receiver software reset is required (cmdr.rres = 1). see chapter 3.7.2 . 00 b , reserved 01 b , cmi (1t2b+hdb3), (optical interface) 10 b , ami (ternary or digital dual-rail interface) 11 b , hdb3 code in e1 or b8zs code in t1/j1 mode (ternary or digital dual-rail interface) exze 3 rw extended hdb3 error detection, e1 only selects error detection mode in e1 mode. in t1/j1 mode this bit is reserved. 0 b , only double violations are detected. 1 b , extended code violation detection: 0000 strings are detected additionally. incrementing of the code violation counter cvc is done after receiving four zeros. errors are indicated by lsr1.exzd = 1. uz ;& uz 5& uz (;=( uz $/0 5hv uz 6,0
octalliu tm pef 22508 e register descriptionmode register 0 data sheet 94 rev. 1.0, 2005-06-02 alm 2 rw alarm mode, e1 only selects the ais alarm detection mode in e1 mode. in t1/j1 mode this bit is reserved. 0 b , the ais alarm is detected according to ets300233. detection: an ais alarm is detected if the incoming data stream contains less than 3 zeros within a period of 512 bits and a loss of frame alignment is indicated. recovery: the alarm is cleared if 3 or more zeros within 512 bits are detected or the fas word is found. 1 b , the ais alarm is detected according to itu-t g.775 detection: an ais alarm is detected if the incoming data stream contains less than 3 zeros in each doubleframe period of two consecutive doubleframe periods (1024 bits). recovery: the alarm is cleared if 3 or more zeros are detected within two consecutive doubleframe periods. sim 0 rw alarm simulation, in e1 mode sim has to be held stable at high or low level for at least one receive clock period before changing it again. 0 b , normal operation. 1 b , initiates internal error simulation of ais, loss-of-signal and code violations. alarm simulation, in t1/j1 mode setting/resetting of sim initiates internal error simulation of ais (blue alarm), loss-of-signal (red alarm) and code violations. the error counter cvc is incremented.the selection of simulated alarms is done by the error simulation counter: lsr2.esc(2:0) which is incremented with each setting of bit sim. for complete checking of the alarm indications eight simulation steps are necessary (lsr2.esc(2:0) = 0 after a complete simulation). sim has to be held stable at high or low level for at least one receive clock period before changing it again. field bits type description
data sheet 95 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionmode register 1 mode register 1 mode register 2 mr1 offset reset value mode register 1 xx1d h 00 h field bits type description pmod 4 rw pcm mode this bit decides between e1 and t1/j1 mode. switching from e1 to t1 or vice versa the device needs up to 20 s to settle up to the internal clocking. 0 b , pcm 30 or e1 mode. 1 b , pcm 24 or t1/j1 mode . xais 0 rw transmit ais towards remote end sends ais on ports xl1, xl2, xoid towards the remote end. the outgoing data stream which can be looped back through the local loop to the system interface is not affected. mr2 offset reset value mode register 2 xx1e h 00 h field bits type description rtm 5 rw receive transparent mode, e1 only for e1 mode this bit must be set to 1 for proper operation. 0 b , reserved 1 b , dais 4 rw disable ais to framer interface this bit must be set to 1for proper operation. 0 b , ais is automatically inserted into the data stream to rdo if octalliu tm is in asynchronous state. 1 b , automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit mr2.sais. 5hv uz 302' 5hv uz ;$,6 5hv uz 570 uz '$,6 5hv uz 3/% 5hv
octalliu tm pef 22508 e register descriptionloop-back register data sheet 96 rev. 1.0, 2005-06-02 loop-back register plb 2 rw payload loop-back see chapter 3.11.5 . 0 b , normal operation. payload loop is disabled. 1 b , the payload loop-back loops the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received on port xdi, xsig, sypx and xmfs is ignored. with xsp.tt0 = 1 time slot 0 is also looped back. if xsp.tt0 = 0 time slot 0 is generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. it is recommended to write the actual value of xc1 into this register once again, because a write access to register xc1 sets the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation (the write operation forces a slip). loop offset reset value loop-back register xx1f h 00 h field bits type description rtm 6 rw receive transparent mode, t1 only for t1/j1 mode this bit must be set to 1 for proper operation. 0 b , reserved 1 b , field bits type description 5hv uz 570 5hv
data sheet 97 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionmode register 4 mode register 4 mode register 5 mr4 offset reset value mode register 4 xx20 h 00 h field bits type description tm 6 rw transparent mode, t1 only for t1/j1 mode this bit must be set to 1 for proper operation. 0 b , reserved 1 b , mr5 offset reset value mode register 5 xx21 h 00 h field bits type description xld/tt0 5 rw xld, transmit line loop-back (llb) down code, t1/j1 only the equivalent bit in e1 mode is mr3.xld. 0 b , normal operation. 1 b , a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is overwritten by the framing/dl/crc bits optionally. tt0, transmit transparent mode, e1 only for proper operation this bit must be set to 1 in e1 mode. 5hv uz 70 5hv 5hv uz ;/'77 uz ;/8 5hv uz ;70 5hv
octalliu tm pef 22508 e register descriptionreceive control 0 data sheet 98 rev. 1.0, 2005-06-02 receive control 0 xlu 4 rw transmit llb up code, t1/j1 only this bit is not valid in e1 mode. the equivalent bit in e1 mode is mr3.xlu. 0 b , normal operation. 1 b , a one in this bit position causes the transmitter to replace normal transmit data with the llb up (activate) code continuously until this bit is reset. the llb up code is optionally overwritten by the framing/dl/crc bits. for proper operation bit mr5.xld must be cleared. xtm 2 rw transmit transparent mode for proper operation this bit must be set to 1. rc0 offset reset value receive control 0 xx24 h 00 h field bits type description rdis 3 rw receive data input sense configures the input polarity of the digital receive inputs. 0 b , in dual rail mode rdi, rdin are active low, in dcim mode roid is active high. 1 b , in dual rail mode rdi, rdin are active high, in dcim mode roid is active low. field bits type description 5hv uz 5',6 5hv
data sheet 99 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptiontransmit pulse mask 0 transmit pulse mask 0 see chapter 3.9.6.1 and chapter 3.9.6.2 . the transmit pulse shape which is defined in itu-t g.703 is output on pins xl1 and xl2. the level of the pulse shape can be programmed by registers xpm(2:0) if xpm2.xpdis is set to 0 to create a custom waveform. if xpm2.xpdis is set to 1, the custom waveform can be programed by the registers txp(16:1) and the register bits of xpm(2:0) are unused with exception of the bits xpm2.xlt, xpm2.daxlt and xpm2.xpdis. in order to get an optimized pulse shape for the external transformers each pulse shape is internally divided into four sub pulse shapes if xpm2.xpdis is set to 0. in each sub pulse shape a programmed 5-bit value defines the level of the analog voltage on pins xl1/2. together four 5-bit values have to be programmed to form one complete transmit pulse shape. the four 5-bit values are sent in the following sequence: xp04 to 00: first pulse shape level xp14 to 10: second pulse shape level xp24 to 20: third pulse shape level xp34 to 30: fourth pulse shape level changing the lsb of each subpulse in registers xpm(2:0) changes the amplitude of the differential voltage on xl1/2 by approximately 80 mv. recommended values for standard applications are given in table 22 and table 23. note that in the special cases were the lbo pulse masks are performed in t1 mode, the programming of the pulse masks is done internally, independent on the settings in xpm(2:0). xpm0 offset reset value transmit pulse mask0 xx26 h 7b h field bits type description xp12 7 rw bit 2 of second pulse shape level xp11 6 rw bit 1 of second pulse shape level xp10 5 rw bit 0 (lsb) of second pulse shape level xp04 4 rw bit 4 (msb) of first pulse shape level xp03 3 rw bit 3 of first pulse shape level xp02 2 rw bit 2 of first pulse shape level xp01 1 rw bit 1 of first pulse shape level xp00 0 rw bit 0 (lsb) of first pulse shape level uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3
octalliu tm pef 22508 e register descriptiontransmit pulse mask 1 data sheet 100 rev. 1.0, 2005-06-02 transmit pulse mask 1 for description see transmit pulse mask 0 transmit pulse mask 2 for description see transmit pulse mask 0 xpm1 offset reset value transmit pulse mask1 xx27 h 03 h field bits type description xp30 7 rw bit 0 (lsb) of fourth pulse shape level xp24 6 rw bit 4 (msb) of third pulse shape level xp23 5 rw bit 3 of third pulse shape level xp22 4 rw bit 2 of third pulse shape level xp21 3 rw bit 1of third pulse shape level xp20 2 rw bit 0 (lsb) of third pulse shape level xp14 1 rw bit 4 (msb) of second pulse shape level xp13 0 rw bit 3 of second pulse shape level xpm2 offset reset value transmit pulse mask2 xx28 h 40 h field bits type description 0 7 r always 0 xlt 6 rw transmit line tristate see also chapter 3.9.1 . 0 b , normal operation 1 b , transmit line xl1 and xl2 are switched into high-impedance state. if this bit is set the transmit line monitor status information is frozen (default value after hardware reset). uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 uz ;3 u uz ;/7 uz '$;/7 uz ;3',6 uz ;3 uz ;3 uz ;3 uz ;3
data sheet 101 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionclear channel register 1 clear channel register 1 the registers ccb(1:3) are only valid in t1/j1 mode. daxlt 5 rw disable automatic tristating of xl1/2 see chapter 3.9.7 . 0 b , normal operation. if a short is detected on pins xl1/2 the transmit line monitor sets the xl1/2 outputs into a high-impedance state. 1 b , if a short is detected on xl1/2 pins automatic setting these pins into a high-impedance (by the xl-monitor) state is disabled. xpdis 4 rw disable xpm values see chapter 3.9.6 . 0 b , xp values from registers xpm(2:0) are used for pulse shaping. 1 b , txp values from registers txp(16:1) are used for pulse shaping. xp34 3 rw bit 4 (msb) of second pulse shape level see chapter 3.9.6.1 . xp33 2 rw bit 3 of fourth pulse shape level xp32 1 rw bit 2 of fourth pulse shape level xp31 0 rw bit 1 of fourth pulse shape level ccb1 offset reset value clear channel register 1 xx2f h 00 h field bits type description ch1 7 rw channel selection bits if ami code is selected, all bits must be set to 1 for proper operation. 0 b , normal operation. bit robbing information and zero code suppression (zcs, b7 stuffing) can change contents of the selected speech/data channel if assigned modes are enabled by bits mr5.eibr and mr0.xc(1:0). 1 b , clear channel mode. contents of selected speech/data channel are not overwritten by internal or external bit robbing and zcs information. transmission of channel assigned signaling and control of pulse-density is applied by the user. ch2 6 ch3 5 ch4 4 ch5 3 ch6 2 ch7 1 ch8 0 field bits type description uz &+ uz &+ uz &+ uz &+ uz &+ uz &+ uz &+ uz &+
octalliu tm pef 22508 e register descriptionsimilar registers data sheet 102 rev. 1.0, 2005-06-02 similar registers registers ccb2 and ccb3 have the same description. the offset addresses are listed in ccbn overview , for layout and bit names refer to clear channel registers mode register 3 only valid in e1 mode. table 35 ccbn overview register short name register long name offset address page number ccb2 clear channel register 2 30 h ccb3 clear channel register 3 31 h table 36 clear channel registers 7 6 5 4 3 2 1 0 ccb1 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ccb2 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 ccb3 ch17 ch18 ch19 ch20 ch21 ch22 ch23 ch24 mr3 offset reset value mode register 3 xx31 h 00 h field bits type description xld 5 rw transmit llb down code, e1 only this bit is not valid in t1/j1 mode. in t1/j1 mode the bis mr5.xld is used instead. 0 b , normal operation. 1 b , a one in this bit position causes the transmitter to replace normal transmit data with the llb down (deactivate) code continuously until this bit is reset. the llb down code is optionally overwritten by the time slot 0 depending on bit lcr1.fllb. xlu 4 rw transmit llb up code, e1 only this bit is not valid in t1/j1 mode. in t1/j1 mode the bit mr5.xlu is used instead. 0 b , normal operation. 1 b , a one in this bit position causes the transmitter to replace normal transmit data with the llb up code continuously until this bit is reset. the llb up code is overwritten by the time slot 0 depending on bit lcr1.fllb. for proper operation bit mr3.xld must be cleared. 5hv uz ;/' uz ;/8 uz &0, 5hv
data sheet 103 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionline interface mode 0 line interface mode 0 cmi 3 rw select cmi precoding, e1 only this bit is not valid in t1/j1 mode. in t1/j1 mode the similar bit for b8zs precoding is dic3.cmi. in e1 mode only valid if cmi code (mr0.xc(1:0) = 01 b ) is selected. this bit defines the cmi precoding and influences transmit and receive data. note: before local loop is selected, hdb3 precoding has to be disabled. 0 b , cmi with hdb3 precoding 1 b , cmi without hdb3 precoding lim0 offset reset value line interface mode 0 xx36 h 00 h field bits type description xfb 7 rw transmit full bauded mode only applicable for dual-rail mode (bit lim1.drs = 1). note: if cmi coding is selected (mr0.xc(1:0) = 01 b ) this bit has to be cleared. 0 b , output signals xdo/xdon are half bauded. 1 b , output signals xdo/xdon are full bauded. xdos 6 rw transmit data out sense note: if cmi coding is selected (mr0.xc(1:0) = 01 b ) this bit has to be cleared. the transmit frame marker xfm is independent of this bit. 0 b , output signals xdo/xdon are active low. output xoid is active high (normal operation). 1 b , output signals xdo/xdon are active high. output xoid is active low. rtrs 5 rw receive termination resistance selection this bit controls the analog switch of the receive line interface. note: if the rlt functionality is selected at one of the multi function ports, a logical equivalence is build out of rtrs and rlt for controlling the analog switch. if rlt functionality is not configured at one of the multi function ports, the analog switch is controlled only by rtrs. 0 b , analog is switched off. 1 b , analog switch is switched on. field bits type description uz ;)% uz ;'26 uz 5756 uz '&,0 5hv uz 5/0 uz // uz 0$6
octalliu tm pef 22508 e register descriptionline interface mode 0 data sheet 104 rev. 1.0, 2005-06-02 dcim 4 rw digital clock interface mode note: dco-x must be used in dcim mode (cmr1.dxja = 0). 0 b , normal operation. 1 b , enables the digital clock interface mode (synchronization interface mode) according to itu-t g.703, section 13. a 2048/1544 khz clock is expected on rl1/2. on xl1/2 a 2048/1544 khz output clock is driven. the transmit clock signal on xl1/2 is derived from the clock supplied on fclkx (cmr1.dxss = 0). rlm 2 rw receive line monitoring see chapter 3.7.4 . 0 b , normal receiver mode 1 b , receiver mode for receive line monitoring; the receiver sensitivity is increased to detect resistively attenuated signals of -20 db (short- haul mode only) ll 1 rw local loop see chapter 3.11.4 . 0 b , normal operation 1 b , local loop active. the local loop back mode disconnects the receive lines rl1/rl2 or roid from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream is transmitted undisturbed on the line. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is transferred through the complete analog receiver. mas 0 rw master mode see also table 19 . 0 b , slave mode 1 b , master mode on. setting this bit the dco-r circuitry is frequency synchronized to the clock (2.048 mhz or 8 khz, see ipc.ssyf) supplied by sync. if this pin is connected to vss or vdd (or left open and pulled up to vdd internally) the dco-r circuitry is centered and no receive jitter attenuation is performed (only if 2.048 mhz clock is selected by resetting bit ipc.ssyf). the generated clocks are stable. field bits type description
data sheet 105 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionline interface mode 1 line interface mode 1 lim1 offset reset value line interface mode 1 xx37 h 80 h field bits type description clos 7 rw clear data in case of los 0 b , normal receiver mode, receive data stream is transferred normally in long-haul mode 1 b , received data is cleared (driven to low level), as soon as los is detected ril2 6 rw receive input threshold only valid if analog line interface is selected (lim1.drs = 0).?no signal? is declared if the voltage between pins rl1 and rl2 drops below the limits programmed by bits ril(2:0) and the received data stream has no transition for a period defined in the pcd register. see dc characteristics for detail. ril1 5 rw ril0 4 rw jatt 2 rw transmit jitter attenuator note: jatt is only used to define the jitter attenuation during remote loop operation. remote loop operation can be set by lim1.rl jitter attenuation during normal operation is not affected by jatt. 0 b , transmit jitter attenuator is disabled for remote loop. transmit data bypasses the remote loop jitter attenuator buffer. 1 b , jitter attenuator is active for remote loop. received data from pins rl1/2 or roid is sent "jitter-free" on ports xl1/2 or xoid. the de- jittered clock is generated by the dco-x circuitry. rl 1 rw remote loop note: rl is logically ord with automatic loop switching by bom messages. 0 b , normal operation. 1 b , remote loop active. drs 0 rw dual-rail select 0 b , the ternary interface is selected. ports rl1/2 and xl1/2 become analog in/outputs. 1 b , the digital dual-rail interface is selected. received data is latched on ports rdip/rdin while transmit data is output on pins xdop/xdon. uz &/26 uz 5,/ uz 5,/ uz 5,/ 5hv uz -$77 uz 5/ uz '56
octalliu tm pef 22508 e register descriptionpulse count detection register data sheet 106 rev. 1.0, 2005-06-02 pulse count detection register pulse count recovery pcd offset reset value pulse count detection register xx38 h 00 h field bits type description pcd 7:0 rw pulse count detection a los alarm is detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable by the pcd register and can be calculated as follows: t = 16 x (n+1); with 0 n 255. the maximum time is: 256 x 16 x 488 ns = 2 ms. every detected pulse resets the internal pulse counter. the counter is clocked with the receive clock rclk. pcr offset reset value pulse count recovery xx39 h 00 h field bits type description pcr 7:0 rw pulse count recovery a los alarm is cleared if a pulse-density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable by the pcr register and can be calculated as follows: m = n+1; with 0 n 255. the time interval starts with the first detected pulse transition. with every received pulse a counter is incremented and the actual counter is compared to the contents of pcr register. if the pulse number is higher or equal to the pcr value the los alarm is reset otherwise the alarm stays active. in this case the next detected pulse transition starts a new time interval. uz 3&' uz 3&5
data sheet 107 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionline interface mode 2 line interface mode 2 lim2 offset reset value line interface mode 2 xx3a h 20 h field bits type description slt1 5 rw receive slicer threshold 00 b , the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 55% of the peak amplitude. 01 b , the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 67% of the peak amplitude (recommended in some t1/j1 applications). 10 b , the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 50% of the peak amplitude (default, recommended in e1 mode). 11 b , the receive slicer generates a mark (digital one) if the voltage at rl1/2 exceeds 45% of the peak amplitude. slt0 4 rw scf 3 rw select corner frequency of dco-r setting this bit reduces the corner frequency of the dco-r circuit by the factor of ten to 0.2 hz. see chapter 3.7.9 . note: reducing the corner frequency of the dco-r circuitry increases the synchronization time before the frequencies are synchronized. elt 2 rw enable loop-timed 0 b , normal operation 1 b , transmit clock is generated from the clock supplied by mclk which is synchronized to the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive and bit cmr1.dxss must be cleared. 5hv uz 6/7 uz 6/7 uz 6&) uz (/7 5hv
octalliu tm pef 22508 e register descriptionloop code register 1 data sheet 108 rev. 1.0, 2005-06-02 loop code register 1 lcr1 offset reset value loop code register 1 xx3b h 00 h field bits type description eprm 7 rw enable pseudo-random binary sequence monitor see chapter 3.11.1 . 0 b , pseudo-random binary sequence (prbs) monitor is disabled. 1 b , prbs is enabled. setting this bit enables incrementing the cec2 error counter with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr1.llbsc is generated. the current status of the prbs synchronizer is indicated by bit lsr2.llbad. xprbs 6 rw transmit pseudo-random binary sequence a one in this bit position enables transmission of a pseudo-random binary sequence to the remote end. depending on bit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 with a maximum-14-zero restriction (itu-t o. 151). see chapter 3.11.1 . ldc 5:4 rw length deactivate (down) code these bits defines the length of the llb deactivate code which is programmable in register lcr2. 00 b , length: 5 bit 01 b , length: 6 bit, 2 bit, 3 bit 10 b , length: 7 bit 11 b , length: 8 bit, 2 bit, 4bit lac 3:2 rw length activate (up) code these bits defines the length of the llb activate code which is programmable in register lcr3. 00 b , length: 5 bit 01 b , length: 6 bit, 2 bit, 3 bit 10 b , length: 7 bit 11 b , length: 8 bit, 2 bit, 4 bit fllb 1 rw framed line loop-back/invert prbs depending on bit lcr1.xprbs this bit enables different functions: lcr1.xprbs = 0: table 37 . note: invert prbs lcr1.xprbs = 1: see table 38 llbp 0 rw line loop-back pattern see chapter 3.11.2 lcr1.xprbs = 0: see table 39 lcr1.xprbs = 1 or lcr1.eprm = 1: see table 40 uz (350 uz ;35%6 uz /'& uz /$& uz )//% uz //%3
data sheet 109 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register description table 37 fllb constant values (case 1) name and description value framed line loop-back/invert prbs the line loop-back code is transmitted including framing bits. llb code overwrites the fs/dl-bits. 0 b framed line loop-back/invert prbs the line loop-back code is transmitted unframed. llb code does not overwrite the fs/dl- bits. 1 b table 38 fllb constant values (case 2) name and description value framed line loop-back/invert prbs the generated prbs is transmitted not inverted. 0 b framed line loop-back/invert prbs the prbs is transmitted inverted. 1 b table 39 llbp constant values (case 1) name and description value line loop-back pattern fixed line loop-back code according to ansi t1. 403. 0 b line loop-back pattern enable user-programmable line loop-back code by register lcr2/3. 1 b table 40 llbp constant values (case 2) name and description value line loop-back pattern 2 15 -1 0 b line loop-back pattern 2 20 -1 1 b
octalliu tm pef 22508 e register descriptionloop code register 2 data sheet 110 rev. 1.0, 2005-06-02 loop code register 2 loop code register 3 lcr2 offset reset value loop code register 2 xx3c h 00 h field bits type description ldc 7:0 rw line loop-back deactivate code if enabled by bit mr3.xld = 1 in e1 or mr5.xld = 1 in t1/j1 mode the llb deactivate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared. if lcr2 is changed while the previous deactivate code has been detected and is still received, bit lsr2.llbdd in e1 or lsr1.llbdd in t1/j1 mode will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). lcr3 offset reset value loop code register 3 3d h 00 h field bits type description lac 7:0 rw line loop-back activate code if enabled by bit mr3.xld = 1 in e1 or mr5.xld = 1 in t1/j1 mode the llb activate code automatically repeats until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmitted last. for correct operations bit lcr1.xprbs has to cleared.if lcr3 is changed while the previous activate code has been detected and is still received, bit lsr2.llbad in e1 or lsr1.llbad in t1/j1 mode will stay active until the incoming signal changes or a receiver reset is initiated (cmdr.rres = 1). uz /'& uz /$&
data sheet 111 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptiondigital interface control 1 digital interface control 1 see chapter 3.7.10 . dic1 offset reset value digital interface control 1 xx3e h 00 h field bits type description rbs 5:4 rw receive buffer size see table 21 . 00 b , buffer size: 2 frames 01 b , buffer size: 1 frame 10 b , buffer size: 96 bits 11 b , bypass of receive elastic store bim 2 rw bit interleaved mode 0 b , byte interleaved mode 1 b , bit interleaved mode xbs 1:0 rw transmit buffer size see table 21 . 00 b , bypass of transmit elastic store 01 b , buffer size: 1 frame 10 b , buffer size: 2 frames 11 b , buffer size: 96 bits 5hv uz 5%6 5hv uz %,0 uz ;%6
octalliu tm pef 22508 e register descriptiondigital interface control 2 data sheet 112 rev. 1.0, 2005-06-02 digital interface control 2 digital interface control 3 dic2 offset reset value digital interface control 2 xx3f h 00 h field bits type description crb 5 rw center receive elastic buffer only applicable if the time slot assigner is disabled (pc(3:1).rpc(3:0) = 0001 b ), no external or internal synchronous pulse receive is generated. a transition from low to high forces a receive slip and the read- pointer of the receive elastic buffer is centered. the delay through the buffer is set to one half of the current buffer size. it should be hold high for at least two 2.048 mhz periods before it is cleared. dic3 offset reset value digital interface control 3 xx40 h 00 h field bits type description cmi 7 rw select cmi precoding (t1 only) only valid if cmi code (mr0.xc(1:0) = 01 b ) is selected. this bit defines the cmi precoding and influences transmit and receive data. note: before local loop is closed, b8zs precoding has to be switched off. 0 b , cmi with b8zs precoding 1 b , cmi without b8zs precoding 5hv uz &5% 5hv uz &0, uz 5575, uz 575, uz )6&7 uz 5(6; uz 5(65 5hv
data sheet 113 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptiondigital interface control 3 rrtri 6 rw rdo tristate mode see chapter 3.7.4 note: rrtri is logically exored with rtdmt multi function port, if this function is selected. rtdmt exor rrtri sets additionally rclk into tristate. 00 b , normal operation (rdop is switched to low level during inactive channel/bit phases). 01 b , rdo is switched into tristate mode during inactive channel/bit phases. 10 b , rdo is tristate constantly (and also rclk). 11 b , rdo is tristate constantly (and also rclk). rtri 5 fsct 4 rw fsc tristate mode 0 b , normal operation of fsc pin. 1 b , fsc is switched into tristate mode. resx 3 rw rising edge synchronous transmit depending on this bit all transmit framer interface data are clocked (outputs) or sampled (inputs) with the selected active edge of the selected framer transmit clock. only valid if cmr2.ixsc = 0: note: cmr2.ixsc = 1: value of resx bit has no impact on the selected edge of the system interface clock but value of resr bit is used as resx. example: if resr = 0, the rising edge of system interface clock is the selected one for sampling data on xdi and vice versa. 0 b , clocked or sampled with the first falling edge of the selected framer interface transmit clock. 1 b , clocked or sampled the first rising edge of the selected framer interface transmit clock. resr 2 rw rising edge synchronous receive depending on this bit all receive framer interface data are clocked (outputs) or sampled (inputs) with the selected active edge. 0 b , clocked or sampled with the first falling edge of the selected framer interface receive clock. 1 b , clocked or sampled with the first rising edge of the selected framer interface receive clock. field bits type description
octalliu tm pef 22508 e register descriptionclock mode register 4 data sheet 114 rev. 1.0, 2005-06-02 clock mode register 4 cmr4 offset reset value clock mode register 4 xx41 h 00 h field bits type description iar 7:3 rw integral parameter selection (corner frequency and attenuation selection) for the dco-r only valid if cmr6.dcocompn = 1and cmr2.ecfar = 1, see chapter 3.7.9 . rs 2:0 rw receive clock (rclk) frequency selection see also chapter 3.7 . 000 b , clock recovered from the line through the dpll drives rclk. 001 b , clock recovered from the line through the dpll drives rclk. logically ord with the incoming los signal. 010 b , 2.048 mhz, dejitered, sourced by dco-r. 011 b , 4.096 mhz, dejitered, sourced by dco-r. 100 b , 8.192 mhz, dejitered, sourced by dco-r. 101 b , 16.384 mhz, dejitered, sourced by dco-r. 110 b , 2.048 mhz logically ord with los. 111 b , 16.384 mhz logically ord with los. uz ,$5 uz 56
data sheet 115 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionclock mode register 5 clock mode register 5 cmr5 offset reset value clock mode register 5 xx42 h 00 h field bits type description drss 7:5 rw dco-r channel selection see chapter 3.7 . 000 b , receive reference clock generated by the dpll of channel 1. 001 b , receive reference clock generated by the dpll of channel 2. 010 b , receive reference clock generated by the dpll of channel 3. 011 b , receive reference clock generated by the dpll of channel 4. 100 b , receive reference clock generated by the dpll of channel 5. 101 b , receive reference clock generated by the dpll of channel 6. 110 b , receive reference clock generated by the dpll of channel 7. 111 b , receive reference clock generated by the dpll of channel 8. iax 4:0 rw integral parameter selection (corner frequency and attenuation selection) for the dco-x only valid if cmr6.dcocompn = 1 and cmr2.ecfax = 1, see chapter 3.7.9 . uz '566 uz ,$;
octalliu tm pef 22508 e register descriptionclock mode register 6 data sheet 116 rev. 1.0, 2005-06-02 clock mode register 6 cmr6 offset reset value clock mode register 6 xx43 h 00 h field bits type description dcocompn 7 rw compatibility programming of dco-r/dco-x disable only applicable if cmr2.ecfar/ecfax is set. see chapter 3.7.9 , table 18 . 0 b , programming of corner frequencies of dco-r/dco-x is done with registers cmr3.cfar (3:0) /cfax(3:0), compatible to the quadliu. register bits cmr5.iax(4:0)/cmr4.iar(4:0) are not valid. 1 b , programming of corner frequencies and attenuation factors of dco-r/dco-x is done with registers cmr3.cfar (3:0)/cfax(3:0) and cmr4.iar(4:0)/cmr5.iax(4:0) in the range 0.2 ... 20 hz. sresr 6 rw soft reset of dco-r by setting this bit a soft reset of the dco-r will be performed: the initial phase error is set to zero and the loop filter is cleared. to enable the dco-r lock functionality, this bit must be cleared subsequently. see chapter 3.7.9 . 0 b , dco-r enabled (normal lock functionality). 1 b , soft reset of dco-r, no lock functionality. sresx 5 rw soft reset of dco-x by setting this bit a soft reset of the dco-x will be performed: the initial phase error is set to zero and the loop filter is cleared. to enable the dco-x lock functionality, this bit must be cleared subsequently. see chapter 3.7.9 . 0 b , dco-x enabled (normal lock functionality). 1 b , soft reset of dco-x, no lock functionality. stf 4:2 rw transmit clock (tclk) frequency selection see chapter 3.9.2 .. note that frequencies are not in ascend ordering. 000 b , 2.048 mhz. 001 b , 8.192 mhz. 010 b , 4.096 mhz. 011 b , 16.384 mhz. 100 b , 32.768 mhz. 101 b , reserved. 110 b , reserved. 111 b , reserved. uz '&2&203 1 uz 65(65 uz 65(6; uz 67) uz 6&); uz $7&6
data sheet 117 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionclock mode register 1 clock mode register 1 scfx 1 rw select corner frequency of dco-x only applicable if cmr2.exfax = 0. see chapter 3.7.9 and chapter 3.9.4 . 0 b , corner frequency of dco-x is 2 hz. 1 b , corner frequency of dco-x is 0.2 hz. atcs 0 rw automatic transmit clock switching see chapter 3.9.3 . if tclk is lost, automatically switching to fclkx can be performed. note: kind of used transmit clock source is shown in status register xclks. 0 b , automatic clock switching is disabled. 1 b , automatic clock switching is enabled. cmr1 offset reset value clock mode register 1 xx44 h 00 h field bits type description dcs 3 rw disable clock-switching in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of loss-of-signal los the dco-r switches automatically to the clock sourced by port sync, see also table 18. 0 b , automatic switching from rclk to sync is enabled 1 b , automatic switching from rclk to sync is disabled dxja 1 rw disable internal transmit jitter attenuation setting this bit disables the transmit jitter attenuation. reading the data out of the transmit elastic buffer and transmitting on xl1/2 (xdop/n/xoid) is done with the clock provided on pin tclk. in transmit elastic buffer bypass mode the transmit clock is taken from fclkx, independent of this bit. field bits type description 5hv uz '&6 5hv uz ';-$ uz ';66
octalliu tm pef 22508 e register descriptionclock mode register 2 data sheet 118 rev. 1.0, 2005-06-02 clock mode register 2 dxss 0 rw dco-x synchronization clock source 0 b , the dco-x circuitry synchronizes to the internal reference clock which is sourced by fclkx/r or rclk. since there are many reference clock opportunities the following internal prioritizing in descending order from left to right is realized: lim1.rl > cmr1.dxss > lim2.elt > current working clock of transmit system interface. if one of these bits is set the corresponding reference clock is taken. 1 b , dco-x synchronizes to an external reference clock provided on multi function port xpa or xpb pin function tclk, if no remote loop is active. tclk is selected by pc(2:1).xpc(3:0) = 0011 b . cmr2 offset reset value clock mode register 2 xx45 h 00 h field bits type description ecfax 7 rw enable corner frequency adjustment for dco-x see chapter 3.7.9 . note: dco-x must be activated. 0 b , adjustment is disabled (only 2 hz and 0.2 hz are possible). 1 b , adjustment is enabled as programmed in cmr3.cfax(3:0) and cmr4.iax(4:0). ecfar 6 rw enable corner frequency adjustment for dco-r see chapter 3.7.9 . note: dco-r must be activated. 0 b , adjustment is disabled (only 2 hz and 0.2 hz are possible). 1 b , adjustment is enabled as programmed in cmr3.cfar(3:0) and cmr5.iar(4:0). dcoxc 5 rw dco-x center-frequency enable see chapter 3.7.9 0 b , the center function of the dco-x circuitry is disabled. 1 b , the center function of the dco-x circuitry is enabled. dco-x centers to 2.048 mhz related to the master clock reference (mclk), if reference clock (e.g. fclkx) is missing. field bits type description uz (&)$; uz (&)$5 uz '&2;& uz '&) uz ,563 uz ,56& 5hv uz ,;6&
data sheet 119 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionclock mode register 2 dcf 4 rw dco-r center- frequency disabled see also table 19 . 0 b , the dco-r circuitry is frequency centered in master mode if no 2.048 mhz reference clock on pin sync is provided or in slave mode if a loss-of-signal occurs in combination with no 2.048 mhz clock on pin sync or a gapped clock is provided on pin rclki and this clock is inactive or stopped. 1 b , the center function of the dco-r circuitry is disabled. the generated clock (dco-r) is frequency frozen in that moment when no clock is available on pin sync or pin rclki. the dco-r circuitry starts synchronization as soon as a clock appears on pins sync or rclki. irsp 3 rw internal receive system frame sync pulse note: recommendation: this bit should be set to 1. 0 b , the frame sync pulse is derived from rdop output signal internally (free running). 1 b , the frame sync pulse for the receive system interface is internally sourced by the dco-r circuitry. this internally generated frame sync signal can be output (active low) on multifunction ports rp(a to d) (rpc(3:0) = 0001 h ). irsc 2 rw internal receive digital (framer) clock see also figure 35 . 0 b , the working clock for the receive framer interface is sourced by fclkr or in receive elastic buffer bypass mode from the corresponding extracted receive clock rclk. 1 b , the working clock for the receive framer interface is sourced internally by dco-r or in bypass mode by the extracted receive clock. fclkr is ignored. ixsc 0 rw internal transmit digital (framer) clock see also figure 35 . 0 b , the working clock for the transmit framer interface is sourced by fclkx. 1 b , the working clock for the transmit framer interface is sourced internally by the working clock of the receive framer interface. fclkx is ignored. field bits type description
octalliu tm pef 22508 e register descriptionglobal configuration register data sheet 120 rev. 1.0, 2005-06-02 global configuration register gcr offset reset value global configuration register 0046 h 00 h field bits type description vis 7 rw masked interrupts visible see also chapter 3.5.3 0 b , masked interrupt status bits are not visible in registers isr(7:0). 1 b , masked interrupt status bits are visible in isr(7:0), but they are not visible in register gis. sci 6 rw status change interrupt 0 b , interrupts are generated either on activation or deactivation of the internal interrupt source. 1 b , the following interrupts are activated both on activation and deactivation of the internal interrupt source: isr2.los, isr2.ais, isr3.lmfa16. pd 0 rw power down switches between power-up and power-down mode. after switching from power down to power up a receiver reset should be made by setting of cmdr.rres. 0 b , power up 1 b , power down: all outputs are driven inactive; multifunction ports are driven high by the weak internal pull-up device. uz 9,6 uz 6&, 5hv uz 3'
data sheet 121 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionclock mode register 3 clock mode register 3 port configuration 1 see chapter 3.12 . cmr3 offset reset value clock mode register 3 xx48 h 00 h field bits type description cfax 7:4 rw corner frequency adjustment for dco-x see chapter 3.7.9 . note: dco-x must be activated and cmr2.ecfax must be set (adjustment must be enabled). cfar 3:0 rw corner frequency adjustment for dco-r see chapter 3.7.9 . note: dco-r must be activated and cmr2.ecfar must be set (adjustment must be enabled). pc1 offset reset value port configuration 1 xx80 h 00 h field bits type description rpc1 7:4 rw receive multifunction port configuration see chapter 3.12 . the multifunction ports rp(a to c) are bidirectional. after reset the ports rpa and rpb are reserved, the port rpc is configured as rclk output. with the selection of the pin function the in/output configuration is also achieved. register pc1 configures port rpa, while pc2 configures port rpb and pc3 configures port rpc. see rpc1 constant values uz &)$; uz &)$5 uz 53& uz ;3&
octalliu tm pef 22508 e register description data sheet 122 rev. 1.0, 2005-06-02 xpc1 3:0 rw transmit multifunction port configuration see chapter 3.12 . the multifunction ports xp(a to b) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. each of the three different input functions (tclk, xlt and xlt ) may only be selected once. no input function must be selected twice or more. register pc1 configures port xpa and pc2 the port xpb. see xpc1 constant values table 41 rpc1 constant values name and description value reserved 0000 b reserved 0001 b reserved 0010 b reserved 0011 b reserved 0100 b reserved 0101 b reserved 0110 b reserved 0111 b rlt: receive line termination (input) ?hardware? switching of receive line termination, see chapter 3.7.3 1000 b gpi: general purpose input value of this input is stored in register mfpi. 1001 b gpoh: general purpose output, high level pin is set fixed to high level 1010 b gpol: general purpose output, low level pin is set fixed to low level 1011 b los: loss of signal loss of signal indication output 1100 b rtdmt: receive tdm tristate (input) receive tdm i/f tristate (rdop, rclk). 1101 b rdon: receive data out negative negative receive data out in dual rail mode or bipolar violation out in liu single rail mode 1110 b rclk: rclk output 1111 b table 42 xpc1 constant values name and description value reserved 0000 b reserved 0001 b reserved 0010 b field bits type description
data sheet 123 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register description registers pc2 to pc3 have the same layout and description, but the 4 lsbs of pc3 are not used because only 2 mfps in transmit direction exists. the bits (3:0) of the register pc3 can be written and read, but are not valid. only one of the ports rpa, rpb or rpc must be configured as rtdmt. only one of the ports xpa or xpb must be configured as xlt or xlt . the registers pc1, pc2 and pc4 have the reset values 00 h , pc3 has the reset value f0 h . the offset addresses are listed in pcn overview , for bit names refer to port configuration registers . tclk: transmit clock (input) a 2.048/8.192 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) is not used. optionally this input is used as a synchronization clock for the dco-x circuitry with a frequency of 2.048 mhz. 0011 b reserved 0100 b reserved 0101 b reserved 0110 b xclk: transmit line clock (output) frequency: 2.048 mhz 0111 b xlt: transmit line tristate control input, high active with a high level on this port the transmit lines xl1/2 or xdop/n are set directly into tristate. this pin function is logically ord with register xpm2.xlt. see chapter 3.9.1 . 1000 b gpi: general purpose input, low level value of this input is stored in register mfpi. 1001 b gpoh: general purpose output, high level pin is set fixed to high level 1010 b gpol: general purpose output, low level pin is set fixed to low level 1011 b reserved 1100 b xdin: transmit data in negative negative transmit data in for dual rail mode 1101 b xlt: transmit line tristate control input, low active see xlt 1110 b reserved 1111 b table 43 pcn overview register short name register long name offset address page number pc2 port configuration register 2 xx81 h pc3 port configuration register 3 xx82 h table 44 port configuration registers 7 6 5 4 3 2 1 0 pc1 rpc13 rpc12 rpc11 rpc10 xpc13 xpc12 xpc11 xpc10 pc2 rpc23 rpc22 rpc21 rpc20 xpc23 xpc22 xpc21 xpc20 pc3 rpc33 rpc32 rpc31 rpc30 xpc33 xpc32 xpc31 xpc30 table 42 xpc1 constant values (cont?d) name and description value
octalliu tm pef 22508 e register descriptionport configuration 5 data sheet 124 rev. 1.0, 2005-06-02 port configuration 5 pc5 offset reset value port configuration 5 xx84 h 00 h field bits type description phdsx 7 rw phase decoder switch for dco-x see formulas in gcm6 . 0 b , switch phase decoder by 1/3 1 b , switch phase decoder by 1/6 phdsr 6 rw phase decoder switch for dco-r see formulas in gcm6 . 0 b , switch phase decoder by 1/3 1 b , switch phase decoder by 1/6 0 2 rw fixed 0 csrp 1 rw configure fclkr port 0 b , fclkr: input 1 b , fclkr: output crp 0 rw configure rclk port 0 b , rclk: input 1 b , rclk: output uz 3+'6; uz 3+'65 5hv uz uz &653 uz &53
data sheet 125 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal port configuration 1 global port configuration 1 port configuration 6 gpc1 offset reset value global port configuration 1 0085 h 00 h field bits type description csfp 6:5 rw configure sec/fsc port the fsc pulse is generated if the dco-r circuitry of the selected channel is active (cmr2.irsc = 1 or cmr1.rs(1:0) = 10 b or 11 b ), see chapter 3.8.4 00 b , sec: input, active high 01 b , sec: output, active high 10 b , fsc: output, active high 11 b , fsc: output, active low pc6 offset reset value port configuration 6 xx86 h 00 h field bits type description tsre 6 rw transmit serial resistor enable note: see table 23 for more details 0 b , internal serial resistors are disabled. 1 b , internal serial resistors are enabled. 5hv uz &6)3 5hv 5hv uz 765( 5hv
octalliu tm pef 22508 e register descriptionglobal port configuration register 2 data sheet 126 rev. 1.0, 2005-06-02 global port configuration register 2 gpc2 offset reset value global port configuration register 2 008a h 00 h field bits type description fss 6:4 rw fsc source selection see chapter 3.8.4 . 000 b , fsc sourced by channel 1. 001 b , fsc sourced by channel 2. 010 b , fsc sourced by channel 3. 011 b , fsc sourced by channel 4. 100 b , fsc sourced by channel 5. 101 b , fsc sourced by channel 6. 110 b , fsc sourced by channel 7. 111 b , fsc sourced by channel 8. r1s 2:0 rw rclk1 source selection see chapter 3.7 . 000 b , rclk1 sourced by channel 1. 001 b , rclk1 sourced by channel 2. 010 b , rclk1 sourced by channel 3. 011 b , rclk1 sourced by channel 4. 100 b , rclk1 sourced by channel 5. 101 b , rclk1 sourced by channel 6. 110 b , rclk1 sourced by channel 7. 111 b , rclk1 sourced by channel 8. 5hv uz )66 5hv uz 56
data sheet 127 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal clock mode register 1 global clock mode register 1 global clock mode register 2 gcm1 offset reset value global clock mode register 1 0092 h 00 h field bits type description phd_e1 7:0 rw frequency adjust for e1 lower 8 bits, for highest 4 bits see gcm2) for details see calculation formulas in register gcm6 and table 45 . gcm2 offset reset value global clock mode register 2 0093 h 10 h field bits type description phsdem 7 rw rx phase decoder demand 0 b , default operation 1 b , see formulas in gcm6 . phsdir 6 rw rx phase decoder direction 0 b , default operation 1 b , see formulas in gcm6 . phsds 5 rw rx phase decoder switch 0 b , default operation 1 b , see formulas in gcm6 . uz 3+'b( uz 3+6'(0 uz 3+6',5 uz 3+6'6 uz 9)5(4b( 1 uz 3+'b(
octalliu tm pef 22508 e register descriptionglobal clock mode register 2 data sheet 128 rev. 1.0, 2005-06-02 vfreq_en 4 rw variable frequency enable if ?fixed mode? mode is selected the clock frequency at the pin mclk must be 2.048 for e1 or 1.544 mhz for t1/j1 respectively. the setting of the whole clock mode is done automatically: register bits of gcm1, gcm2.phsdem, phdir, phsds, phd_e1 and gcm3 to gcm8 are unused. if ?fixed mode? mode is selected and the spi- or sci-interface is used as controller interface, the pinstrapping values at d(15:5) are also not used. see also chapter 3.5.5 . note: if ?fixed mode ? is enabled all of the eight ports must work in the same mode, either in t1 or in e1 mode. a switching between e1 and t1 modes causes a reset of the whole clock system. if ?fixed mode? is disabled a switching between e1 and t1 mode (which can be done in this case individually for every port) causes not a reset of the whole clock system. 0 b , fixed clock frequency of 2.048 (e1) or 1.544 mhz (t1/j1) 1 b , variable master clock frequency (normal operation, operation after reset) phd_e1 3:0 rw frequency adjust for e1 (highest 4 bits, for lower 8 bits see gcm1) the 12 bit frequency adjust value is in the decimal range of -2048 to +2047. negative values are represented in 2s-complement format. for details see calculation formulas in register gcm6 and table 45 . 100000000000 b , -2048 ....................... b , 000000000000 b , 0 ...................... b , 011111111111 b , +2047 field bits type description
data sheet 129 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal clock mode register 3 global clock mode register 3 global clock mode register 4 gcm3 offset reset value global clock mode register 3 0094 h 00 h field bits type description phd_t1 7:0 rw frequency adjust for t1 (lower 8 bits, for highest 4 bits see gcm4) the 12 bit frequency adjust value is in the decimal range of -2048 to +2047. negative values are represented in 2s-complement format. for details see calculation formulas in register gcm6 and table 45 . 100000000000 b , -2048 ....................... b , 000000000000 b , 0 ...................... b , 011111111111 b , +2047 gcm4 offset reset value global clock mode register 4 0095 h 00 h field bits type description dvm_t1 7:5 rw divider mode for t1 this bits can be write and read to be software compatible to quadliu, but has no influence on the clock system uz 3+'b7 uz '90b7 5hv uz 3+'b7
octalliu tm pef 22508 e register descriptionglobal clock mode register 5 data sheet 130 rev. 1.0, 2005-06-02 global clock mode register 5 phd_t1 3:0 rw frequency adjust for t1 (highest 4 bits, for lower 8 bits see gcm3) the 12 bit frequency adjust value is in the decimal range of -2048 to +2047. negative values are represented in 2s-complement format. for details see calculation formulas in register gcm6 and table 45 . 100000000000 b , -2048 ....................... b , 000000000000 b , 0 ...................... b , 011111111111 b , +2047 gcm5 offset reset value global clock mode register 5 0096 h 00 h field bits type description mclk_low 7 rw master clock range low this bit can be write and read to be software compatible to quadliu, but has no influence on the clock system. pll_m 4:0 rw pll dividing factor m for details see calculation formulas in register gcm6 and table 45 . 00001 b , 1 ......... b , 11111 b , 31 field bits type description uz 0&/.b/2 : 5hv uz 3//b0
data sheet 131 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal clock mode register 6 global clock mode register 6 flexible clock mode settings if ?flexible master clock mode? is used (vfreq_en = 1), the according register settings can be calculated as follows (a windows-based program for automatic calculation is available, see chapter 8.3 . for some of the standard frequencies see the table below. 1. the master clock mclk must be in the following frequency range: 1.02 mhz f mclk 20 mhz 2. generally the pll of the master clocking unit includes an input divider with a dividing factor pll_m +1 and a feedback divider with a dividing factor 4 x (pll_n +1). so it generates a clock f pll of about f pll = f mclk x 4 x (pll_n +1) / (pll_m +1) . 3. the selection of pll_n and pll_m must be done in the following way: the pll frequency f pll must be in the following range: 200 mhz f pll 300 mhz . the combinations of the values pll_m and pll_m must fulfill the equations: 2 mhz f mclk / (pll_m +1) 6 mhz , if pll_n is in the range 25 to 63. 5 mhz f mclk / (pll_m +1) 15 mhz , if pll_n is in the range 1 to 24. 4. in e1 mode, the selection of phsn_e1 and phsx_e1 must be done in such a manner that the frequency for the receiver f rx_e1 has nearly the value 16 x f data_e1 x (1 + 100ppm) = 32.7713 mhz: f rx_e1 = f pll / {phsn_e1 + (phsx_e1 / 6)} . in t1/j1 mode, the selection of phsn_t1 and phsx_t1 must be done in such a manner that the frequency for the receiver f rx_t1 has nearly the value 16 x f data_t1 x (1 + 100ppm) = 24.706 mhz: f rx_t1 = f pll / {phsn_t1 + (phsx_t1 / 6)} . gcm2.phsdem, gcm2.phsdir, gcm2.phsds, pc5.phdsx and pc5.phdsr must be left to 0 5. to bring the ?characteristic e1 frequency? f oute1 exact to 16 x f data_e1 = 32.7680 mhz a correction value phd_e1 is necessary: phd_e1 = round ( 12288 x { [phsn_e1 + (phsx_e1 / 6)] - [ f pll / (16 x f data_e1 )] } ) . gcm6 offset reset value global clock mode register 6 0097 h 00 h field bits type description pll_n 4:0 rw pll dividing factor n for details see calculation formulas below and table 45 . 000001 b , 1 ........... b , 111111 b , 63 5hv uz 3//b1
octalliu tm pef 22508 e register descriptionglobal clock mode register 7 data sheet 132 rev. 1.0, 2005-06-02 to bring the ?characteristic t1 frequency? f outt1 exact to 16 x f data_t1 = 24.704 mhz a correction value phd_t1 is necessary: phd_t1 = round ( 12288 x { [phsn_t1 + (phsx_t1 / 6)] - [ f pll / (16 x f data_t1 )] } ) . example: f mclk = 2.048 mhz pll_n = 33; pll_m = 0 : f pll = 278.528 mhz phsn_e1 = 8; phsn_e1 = 2: f rx_e1 = 33.42 mhz phd_e1 = -2048: f oute1 = 32.768 mhz global clock mode register 7 table 45 clock mode register settings for e1 or t1/j1 fmclk [mhz] gcm1 gcm2 gcm3 gcm4 gcm5 gcm6 gcm7 gcm8 1.5440 f0 h 19 h 00 h 08 h 00 h 2b h 98 h da h 2.0480 00 h 18 h d2 h 0a h 00 h 21 h a8 h 9b h 8.1920 00 h 18 h d2 h 0a h 03 h 21 h a8 h 9b h 12.3520 f0 h 19 h 00 h 08 h 07 h 2b h 98 h da h 16.3840 00 h 18 h d2 h 0a h 07 h 21 h a8 h 9b h gcm7 offset reset value global clock mode register 7 0098 h 80 h field bits type description 1 7 r fixed 1 phsx_e1 6:4 rw frequency adjustment value e1 for details see calculation formulas in register gcm6 and table 45 . 000 b , 0 ...... b , 101 b , 5 phsn_e1 3:0 rw frequency adjustment value e1 for details see calculation formulas in register gcm6 and table 45 . 0001 b , 1 ...... b , 1111 b , 15 u uz 3+6;b( uz 3+61b(
data sheet 133 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal clock mode register 7 global clock mode register 7 global interrupt mask register gcm8 offset reset value global clock mode register 7 0099 h 80 h field bits type description 1 7 r fixed 1 phsx_t1 6:4 rw frequency adjustment value t1 for details see calculation formulas in register gcm6 and table 45 . 000 b , 0 ...... b , 101 b , 5 phsn_t1 3:0 rw frequency adjustment value t1 for details see calculation formulas in register gcm6 and table 45 . 0001 b , 1 ....... b , 1111 b , 15 gimr offset reset value global interrupt mask register 00a7 h ff h field bits type description plll 0 rw pll locked interrupt mask 0 b , gis2.plllc is enabled. 1 b , gis2.plllc is disabled. u uz 3+6;b7 uz 3+61b7 5hv uz 3///
octalliu tm pef 22508 e register descriptiontest pattern control register 0 data sheet 134 rev. 1.0, 2005-06-02 test pattern control register 0 see chapter 3.11.1 . tx pulse template register 1 see chapter 3.9.6.1 and chapter 3.9.6.2 . this register contains the transmit amplitude of the 1st 1/16 of the transmit pulse. the contents of this register is ignored unless bit xpm2.xpdis is set. by default, the values programmed in xpm0 to xpm2 are used to control the transmit pulse template. similar registers registers txp1to txp16 have the same description and layout. every register txpn defines the amplitude of the part n of 16 of the transmit pulse. an overview is given is the next table. note that the reset values of the registers txp1 to txp8 are 38 h , that of the registers txp9 to txp16 are 00 h . tpc0 offset reset value test pattern control register 0 xxa8 h 00 h field bits type description prp 5:4 rw prbs pattern selection 00 b , prbs11 pattern. 01 b , prbs15 pattern. 10 b , prbs20 pattern. 11 b , prbs23 pattern. txp1 offset reset value tx pulse template register 1 xxc1 h 00 h field bits type description txp1 6:0 rw transmit pulse amplitude twos complement number of pulse amplitude, see table 25 and table 26 5hv uz 353 5hv 5hv uz 7;3
data sheet 135 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal port configuration register 3 global port configuration register 3 see chapter 3.7 . table 46 txp overview register short name register long name offset address page number txp2 tx pulse template register 2 xxc2 h txp3 tx pulse template register 3 xxc3 h txp4 tx pulse template register 4 xxc4 h txp5 tx pulse template register 5 xxc5 h txp6 tx pulse template register 6 xxc6 h txp7 tx pulse template register 7 xxc7 h txp8 tx pulse template register 8 xxc8 h txp9 tx pulse template register 9 xxc9 h txp10 tx pulse template register 10 xxca h txp11 tx pulse template register 11 xxcb h txp12 tx pulse template register 12 xxcc h txp13 tx pulse template register 13 xxcd h txp14 tx pulse template register 14 xxce h txp15 tx pulse template register 15 xxcf h txp16 tx pulse template register 16 xxd0 h gpc3 offset reset value global port configuration register 3 00d3 h 21 h field bits type description r3s 6:4 rw rclk3 source selection 000 b , rclk3 sourced by channel 1. 001 b , rclk3 sourced by channel 2. 010 b , rclk3 sourced by channel 3. 011 b , rclk3 sourced by channel 4. 100 b , rclk3 sourced by channel 5. 101 b , rclk3 sourced by channel 6. 110 b , rclk3 sourced by channel 7. 111 b , rclk3 sourced by channel 8. 5hv uz 56 5hv uz 56
octalliu tm pef 22508 e register descriptionglobal port configuration register 4 data sheet 136 rev. 1.0, 2005-06-02 global port configuration register 4 see chapter 3.7 . r2s 2:0 rw rclk2 source selection 000 b , rclk2 sourced by channel 1. 001 b , rclk2 sourced by channel 2. 010 b , rclk2 sourced by channel 3. 011 b , rclk2 sourced by channel 4. 100 b , rclk2 sourced by channel 5. 101 b , rclk2 sourced by channel 6. 110 b , rclk2 sourced by channel 7. 111 b , rclk2 sourced by channel 8. gpc4 offset reset value global port configuration register 4 00d4 h 43 h field bits type description r5s 6:4 rw rclk5 source selection 000 b , rclk5 sourced by channel 1. 001 b , rclk5 sourced by channel 2. 010 b , rclk5 sourced by channel 3. 011 b , rclk5 sourced by channel 4. 100 b , rclk5 sourced by channel 5. 101 b , rclk5 sourced by channel 6. 110 b , rclk5 sourced by channel 7. 111 b , rclk5 sourced by channel 8. r4s 2:0 rw rclk4 source selection 000 b , rclk4 sourced by channel 1. 001 b , rclk4 sourced by channel 2. 010 b , rclk4 sourced by channel 3. 011 b , rclk4 sourced by channel 4. 100 b , rclk4 sourced by channel 5. 101 b , rclk4 sourced by channel 6. 110 b , rclk4 sourced by channel 7. 111 b , rclk4 sourced by channel 8. field bits type description 5hv uz 56 5hv uz 56
data sheet 137 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionglobal port configuration register 5 global port configuration register 5 see chapter 3.7 . gpc5 offset reset value global port configuration register 5 00d5 h 65 h field bits type description r7s 6:4 rw rclk7 source selection 000 b , rclk7 sourced by channel 1. 001 b , rclk7 sourced by channel 2. 010 b , rclk7 sourced by channel 3. 011 b , rclk7 sourced by channel 4. 100 b , rclk7 sourced by channel 5. 101 b , rclk7 sourced by channel 6. 110 b , rclk7 sourced by channel 7. 111 b , rclk7 sourced by channel 8. r6s 2:0 rw rclk6 source selection 000 b , rclk6 sourced by channel 1. 001 b , rclk6 sourced by channel 2. 010 b , rclk6 sourced by channel 3. 011 b , rclk6 sourced by channel 4. 100 b , rclk6 sourced by channel 5. 101 b , rclk6 sourced by channel 6. 110 b , rclk6 sourced by channel 7. 111 b , rclk6 sourced by channel 8. 5hv uz 56 5hv uz 56
octalliu tm pef 22508 e register descriptionglobal port configuration register 6 data sheet 138 rev. 1.0, 2005-06-02 global port configuration register 6 see chapter 3.7 . in-band loop detection time register gpc6 offset reset value global port configuration register 6 00d6 h 07 h field bits type description r8s 2:0 rw rclk8 source selection 000 b , rclk8 sourced by channel 1. 001 b , rclk8 sourced by channel 2. 010 b , rclk8 sourced by channel 3. 011 b , rclk8 sourced by channel 4. 100 b , rclk8 sourced by channel 5. 101 b , rclk8 sourced by channel 6. 110 b , rclk8 sourced by channel 7. 111 b , rclk8 sourced by channel 8. inbldtr offset reset value in-band loop detection time register 00d7 h 00 h field bits type description inbldr 5:4 rw in-band loop detection time for line side see chapter 3.11.2 . 00 b , at least 16 consecutive in-band loop pattern must be valid for detection and to perform automatic loop switching. 01 b , at least 32 consecutive in-band loop pattern must be valid for detection and to perform automatic loop switching. 10 b , in-band loop pattern must be valid for at least 4 seconds for detection and to perform automatic loop switching. 11 b , in-band loop pattern must be valid for at least 5 seconds for detection and to perform automatic loop switching. 5hv uz 56 5hv uz ,1%/'5 5hv
data sheet 139 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionautomatic loop switching register automatic loop switching register enabling of automatic loop switching by in-band loop codes, see chapter 3.11.2 , is performed by this register. interrupt mask register 7 masks interrupt bits of register isr7. als offset reset value automatic loop switching register xxd9 h 00 h field bits type description lils 0 rw line in-band loop switching (remote loop) this bit controls if automatic switching of the remote loop will be done by in-band loop codes from the line side, see chapter 3.11.2 . note: generation of an interrupt when loop up or down code is detected can be selected by demasking (register imr6). setting both, sils and lils to 1 is forbidden. 0 b , automatic switching of remote loop (?on line side?) is disabled (default). 1 b , automatic switching of remote loop (?on line side?) by in-band loop codes detected from the line side is enabled if local loop is not activated by lim0.ll = 1. imr7 offset reset value interrupt mask register 7 xxdf h 00 h field bits type description xclkss1 4 rw xclkss1 interrupt masking 0 b , isr7.xclkss1 is enabled. 1 b , isr7.xclkss1 is disabled xclkss0 3 rw xclkss0 interrupt masking 0 b , isr7.xclkss0 is enabled. 1 b , isr7.xclkss0 is disabled 5hv uz /,/6 5hv uz ;&/.66 uz ;&/.66 5hv
octalliu tm pef 22508 e register descriptionliu mode register 3 data sheet 140 rev. 1.0, 2005-06-02 liu mode register 3 4.1.2 status registers receive buffer delay lim3 offset reset value liu mode register 3 xxe2 h 00 h field bits type description drr 1 rw dual-rail mode on digital side, receive direction 0 b , single rail mode on framer receive side. 1 b , dual rail mode on framer receive side. drx 0 rw dual-rail mode on digital side, transmit direction 0 b , single rail mode on framer transmit side. 1 b , dual rail mode on framer transmit side. rbd offset reset value receive buffer delay xx49 h 00 h field bits type description rbd 5:0 r receive elastic buffer delay these bits informs the user about the current delay (in time slots) through the receive elastic buffer. the delay is updated every 512 or 256 bits (dic1.rbs(1:0)). before reading this register the user has to set bit dec.drbd in order to halt the current value of this register. after reading rbd updating of this register is enabled. not valid if the receive buffer is bypassed. 000000 b , delay < 1 time slot ... b , 111111 b , delay > 63 time slot 5hv uz '55 uz '5; 5hv u 5%'
data sheet 141 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionversion status register version status register receive equalizer status vstr offset reset value version status register 004a h h field bits type description vstr 7:0 r version number of chip the value is 20 h . res offset reset value receive equalizer status xx4b h 00 h field bits type description ev 7:6 r equalizer status valid these bits informs the user about the current state of the receive equalization network. 00 b , equalizer status not valid, still adapting 01 b , equalizer status valid 10 b , equalizer status not valid 11 b , equalizer status valid but high noise floor res 4:0 r receive equalizer status the current line attenuation status in steps of about 1.7 db for e1 and 1.4 db for t1/j1 mode are displayed in these bits. only valid if bits ev(1:0) = 01 b . accuracy: 2 digits, based on temperature influence and noise amplitude variations. 00000 b , minimum attenuation: 0 db ... b , 11001 b , maximum attenuation: -43 db (e1), -36 db (t1/j1) u 9675 u (9 5hv u 5(6
octalliu tm pef 22508 e register descriptionline status register 0 data sheet 142 rev. 1.0, 2005-06-02 line status register 0 lsr0 offset reset value line status register 0 xx4c h 00 h field bits type description los 7 r loss-of-signal ? detection: this bit is set when the incoming signal has ?no transitions? (analog interface) or logical zeros (digital interface) in a time interval of t consecutive pulses, where t is programmable by register pcd. total account of consecutive pulses: 16 t 4096. analog interface: the receive signal level where ?no transition? is declared is defined by the programmed value of lim1.ril(2:0). ? recovery: analog interface: the bit is reset in short-haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril(2:0)) for at least m pulse periods defined by register pcr in the pcd time interval. in long-haul mode additionally bit res.6 must be set for at least 250 s. digital interface: the bit is reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) is set. the bit is also set during alarm simulation and reset, if mr0.sim is cleared and no alarm condition exists. ais 6 r alarm indication signal the function of this bit is determined by mr0.alm. ? mr0.alm = 0: this bit is set when two or less zeros in the received bit stream are detected in a time interval of 250 ms and the octalliu tm is in asynchronous state (lsr0.lfa = 1). the bit is reset when no alarm condition is detected (according to etsi standard). ? mr0.alm = 1: this bit is set when the incoming signal has two or less zeros in each of two consecutive double frame period (512 bits). this bit is cleared when each of two consecutive doubleframe periods contain three or more zeros or when the frame alignment signal fas has been found. (itu-t g.775) the bit is also set during alarm simulation and reset if mr0.sim is cleared and no alarm condition exists.with the rising edge of this bit an interrupt status bit (isr2.ais) is set. u /26 u $,6 5hv
data sheet 143 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionline status register 1 line status register 1 lsr1 offset reset value line status register 1 xx4d h xx h field bits type description exzd 7 r excessive zeros detected significant only, if excessive zero detection has been enabled (mr0.exze = 1). set after detection of more than 3 (hdb3 code) or 15 (ami code) contiguous zeros in the received data stream.this bit is cleared on read. pden 6 r pulse-density violation detected the pulse-density of the received data stream is below the requirement defined by ansi t1. 403 or more than 14 consecutive zeros are detected. with the violation of the pulse-density this bit is set and remains active until the pulse-density requirement is fulfilled for 23 consecutive "1"- pulses. additionally an interrupt status isr0.pden is generated with the rising edge of pden. llbdd 4 r line loop-back deactivation signal detected, only valid in t1 mode in e1 mode the equivalent bit is lsr2.llbdd. this bit is set in case of the llb deactivate signal is detected and then received over a period of more than 33,16 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation.any change of this bit causes an llbsc interrupt. llbad 3 r line loop-back activation signal detected, only valid in t1 mode in e1 mode the equivalent bit is lsr2.llbad. depending on bit lcr1.eprm the source of this status bit changed. ? lcr1.eprm = 0: this bit is set in case of the llb activate signal is detected and then received over a period of more than 33,16 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. ? lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a bit error rate of up to 10 -3 . a data stream containing all zeros or all ones with/without framing bits is also a valid pseudo-random binary sequence. u (;=' u 3'(1 5hv u //%'' u //%$' 5hv u ;/6 u ;/2
octalliu tm pef 22508 e register descriptionline status register 3 data sheet 144 rev. 1.0, 2005-06-02 line status register 3 xls 1 r transmit line short see chapter 3.9.7 . significant only if the ternary line interface is selected by lim1.drs = 0. 0 b , normal operation. no short is detected. 1 b , the xl1 and xl2 are shortened for at least 3 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high-impedance state if bit xpm2.daxlt is reset. after 128 consecutive pulse periods the outputs xl1/2 are activated again and the internal transmit current limiter is checked. if a short between xl1/2 is still further active the outputs xl1/2 are in high- impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit is reset. with any change of this bit an interrupt isr1.xlsc is generated. in case of xpm2.xlt is set this bit is frozen. xlo 0 r transmit line open see also chapter 3.9.7 . 0 b , normal operation 1 b , this bit is set if at least 32 consecutive zeros were sent on pins xl1/xl2 or xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc is set. in case of xpm2.xlt is set this bit is frozen. lsr3 offset reset value line status register 3 xx4e h xx h field bits type description esc 7:5 r error simulation counter, t1 only this three-bit counter is incremented by setting bit mr0.sim. the state of the counter determines the function to be tested. for complete checking of the alarm indications, eight simulation steps are necessary (lsr3.esc = 000 b after a complete simulation). field bits type description u (6& 5hv
data sheet 145 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register description some of these alarm indications are simulated only if the octalliu tm is configured in the appropriate mode. at simulation steps 0, 3, 4, and 7 pending status flags are reset automatically and clearing of the error counters and interrupt status registers isr(7:0) should be done. incrementing the simulation counter should not be done at time intervals shorter than 1.5 ms (f4, f12, f72) or 3 ms (esf). otherwise, reactions of initiated simulations might occur at later steps. control bit fmr0.sim has to be held stable at high or low level for at least one receive clock period before changing it again. table 47 alarm simulation states tested alarms esc(2:0) = 0 1 2 3 4 5 6 7 lfa x x lmfa x x rra (bit2 = 0) x rra (s-bit frame 12) x rra (dl-pattern) x los 1) 1) only active during fmr0.sim = 1 x x x ebc 2) (f12,f72) 2) fec is counting +2 while ebc is counting +1 if the framer is in synchronous state; if asynchronous in state 2 but synchronous in state 6, counters are incremented during state 6 x (x) ebc 2) (only esf) x x x (x) ais 1) x x x x fec 2) x (x) cvc x x x cec (only esf) x x x x rsp x rsn x xsp x xsn x bec 1) x x x coec x x
octalliu tm pef 22508 e register descriptionline status register 2 data sheet 146 rev. 1.0, 2005-06-02 line status register 2 lsr2 offset reset value line status register 2 xx4f h xx h field bits type description llbdd 4 r line loop-back deactivation signal detected, only valid in e1 mode in t1/j1 mode the equivalent bit is lsr1.llbdd. this bit is set in case of the llb deactivate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the time slot 0 is not taken into account for the error rate calculation.any change of this bit causes an llbsc interrupt. llbad 3 r line loop-back activation signal detected, only valid in e1 mode in t1/j1 mode the equivalent bit is lsr1.llbad. depending on bit lcr1.eprm the source of this status bit changed. ? lcr1.eprm = 0: this bit is set in case of the llb activate signal is detected and then received over a period of more than 25 ms with a bit error rate less than 10 -2 . the bit remains set as long as the bit error rate does not exceed 10 -2 . if framing is aligned, the time slot 0 is not taken into account for the error rate calculation. any change of this bit causes an llbsc interrupt. ? lcr1.eprm = 1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a bit error rate of 10 -1 . a data stream containing all zeros or all ones with/without framing bits is also a valid pseudo-random binary sequence. 5hv u //%'' u //%$' 5hv
data sheet 147 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptioncode violation counter lower byte code violation counter lower byte cvcl offset reset value code violation counter lower byte xx52 h 00 h field bits type description cv7 7 r code violations if the hdb3 or the cmi code with hdb3-precoding is selected, the 16-bit counter is incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit mr0.extd. if simple ami coding is enabled (mr0.rc(1:0) = 01 b ) all bipolar violations are counted. the error counter does not roll over.during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit mr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is reset automatically with reading the error counter high byte. if mr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. cv6 6 r cv5 5 r cv4 4 r cv3 3 r cv2 2 r cv1 1 r cv0 0 r u &9 u &9 u &9 u &9 u &9 u &9 u &9 u &9
octalliu tm pef 22508 e register descriptioncode vi olation counter higher byte data sheet 148 rev. 1.0, 2005-06-02 code violation counter higher byte cvch offset reset value code violation counter higher byte xx53 h 00 h field bits type description cv15 7 r code violations if the hdb3 or the cmi code with hdb3-precoding is selected, the 16-bit counter is incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit mr0.extd. if simple ami coding is enabled (mr0.rc(1:0) = 01 b ) all bipolar violations are counted. the error counter does not roll over.during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit mr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dcvc is reset automatically with reading the error counter high byte. if mr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. cv14 6 r cv13 5 r cv12 4 r cv11 3 r cv10 2 r cv9 1 r cv8 0 r u &9 u &9 u &9 u &9 u &9 u &9 u &9 u &9
data sheet 149 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionprbs bit error counter lower bytes prbs bit error counter lower bytes becl offset reset value prbs bit error counter lower bytes xx58 h 00 h field bits type description bec7 7 r prbs bit error counter if the prbs monitor is enabled by lcr1.eprm = 1 this 16-bit counter is incremented with every received prbs bit error in the prbs synchronous state lsr1.llbad = 1. the error counter does not roll over.during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit mr1.ecm.if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the prbs bit error counter bit dec.dbec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dbec is automatically reset with reading the error counter high byte. if mr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. bec6 6 r bec5 5 r bec4 4 r bec3 3 r bec2 2 r bec1 1 r bec0 0 r u %(& u %(& u %(& u %(& u %(& u %(& u %(& u %(&
octalliu tm pef 22508 e register descriptionprbs bit error counter higher bytes data sheet 150 rev. 1.0, 2005-06-02 prbs bit error counter higher bytes bech offset reset value prbs bit error counter higher bytes xx59 h 00 h field bits type description bec15 7 r prbs bit error counter if the prbs monitor is enabled by lcr1.eprm = 1 this 16-bit counter is incremented with every received prbs bit error in the prbs synchronous state lsr1.llbad = 1. the error counter does not roll over.during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit mr1.ecm.if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the prbs bit error counter bit dec.dbec has to be set. with the rising edge of this bit updating the buffer is stopped and the error counter is reset. bit dec.dbec is automatically reset with reading the error counter high byte. if mr1.ecm is set every second (interrupt isr3.sec) the error counter is latched and then automatically reset. the latched error counter state should be read within the next second. bec14 6 r bec13 5 r bec12 4 r bec11 3 r bec10 2 r bec9 1 r bec8 0 r u %(& u %(& u %(& u %(& u %(& u %(& u %(& u %(&
data sheet 151 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptioninterrupt status register 1 interrupt status register 1 all bits are reset when isr1 is read. if bit gcr.vis is set, interrupt statuses in isr1 are flagged although they are masked by register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis, see chapter 3.5.3 . isr1 offset reset value interrupt status register 1 xx69 h 00 h field bits type description llbsc 7 rsc line loop-back status change, e1 only in t1/j1 mode this bit is not valid and isr3.llbsc is used instead. depending on bit lcr1.eprm the source of this interrupt status changed: ? lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal, respectively, is detected over a period of 25 ms with a bit error rate less than 10 -2 . the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 10 -2 . the actual detection status can be read from the lsr2.llbad / lsr2.llbdd in e1 or lsr1.llbad / lsr1.llbdd in t1/j1 mode, respectively. ? prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in lsr2.llbad (e1) or lsr1.llbad (t1/j1). xlsc 1 rsc transmit line status change xlsc is set with the rising edge of the bit lsr1.xlo or with any change of bit lsr1.xls. the actual status of the transmit line monitor can be read from the lsr1.xls and lsr1.xlo. uvf //%6& 5hv uvf ;/6& 5hv
octalliu tm pef 22508 e register descriptioninterrupt status register 2 data sheet 152 rev. 1.0, 2005-06-02 interrupt status register 2 all bits are reset when isr2 is read. if bit gcr.vis is set, interrupt statuses in isr2 are flagged although they are masked by register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. see chapter 3.5.3 interrupt status register 3 all bits are reset when isr3 is read. if bit gcr.vis is set, interrupt statuses in isr3 are flagged although they are masked by register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis, see chapter 3.5.3 . isr2 offset reset value interrupt status register 2 xx6a h 00 h field bits type description ais 3 r alarm indication signal (blue alarm) this bit is set when an alarm indication signal is detected and bit lsr0.ais is set. if gcr.sci is set high this interrupt status bit is activated with every change of state of lsr0.ais.it is set during alarm simulation. los 2 r loss-of-signal (red alarm) this bit is set when a loss-of-signal alarm is detected in the received data stream and lsr0.los is set. if gcr.sci is set high this interrupt status bit is activated with every change of state of lsr0.los. it is set during alarm simulation. isr3 offset reset value interrupt status register 3 xx6b h 00 h field bits type description sec 6 rsc second timer the internal one-second timer has expired. the timer is derived from clock rclk or external pin sec/fsc. 5hv u $,6 u /26 5hv 5hv uvf 6(& 5hv uvf //%6& 5hv uvf 561 ufv 563
data sheet 153 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptioninterrupt status register 4 interrupt status register 4 all bits are reset when isr4 is read. if bit gcr.vis is set, interrupt statuses in isr4 are flagged although they are masked by register imr4. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis, see chapter 3.5.3 . llbsc 3 rsc line loop-back status change, t1/j1 only in e1 mode this bit is not valid and isr1.llbsc is used instead. depending on bit lcr1.eprm the source of this interrupt status changed: ? lcr1.eprm = 0: this bit is set, if the llb activate signal or the llb deactivate signal, respectively, is detected over a period of 25 ms with a bit error rate less than 10 -2 . the llbsc bit is also set, if the current detection status is left, i.e., if the bit error rate exceeds 10 -2 . the actual detection status can be read from the lsr2.llbad / lsr2.llbdd in e1 or lsr1.llbad / lsr1.llbdd in t1/j1 mode, respectively. ? prbs status change lcr1.eprm = 1: with any change of state of the prbs synchronizer this bit is set. the current status of the prbs synchronizer is indicated in lsr2.llbad (e1) or lsr1.llbad (t1/j1). rsn 1 rsc receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 2.048 mhz. a frame is skipped. it is set during alarm simulation. see chapter 3.7.10 . rsp 0 rcs receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 2.048 mhz. a frame is repeated. it is set during alarm simulation. see chapter 3.7.10 . isr4 offset reset value interrupt status register 4 xx6c h 00 h field bits type description xsp 7 rsc transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame is repeated. after a slip has performed writing of register xc1 is not necessary. field bits type description uvf ;63 uvf ;61 5hv
octalliu tm pef 22508 e register descriptionglobal interrupt status register data sheet 154 rev. 1.0, 2005-06-02 global interrupt status register this status register points to pending interrupts sourced by isr(1:4) and isr(6:7), see chapter 3.5.3 . xsn 6 rsc transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame is skipped. after a slip has performed writing of register xc1 is not necessary. gis offset reset value global interrupt status register xx6e h 00 h field bits type description isr7 7 rsc interrupt status register 7 pointer 0 b , no interrupt is pending in isr6. 1 b , at least one interrupt is pending in isr6. isr6 6 rsc interrupt status register 6 pointer 0 b , no interrupt is pending in isr6. 1 b , at least one interrupt is pending in isr6. isr5 5 rsc interrupt status register 5 pointer always 0, because no isr5 exists isr4 4 rsc interrupt status register 4 pointer 0 b , no interrupt is pending in isr4. 1 b , at least one interrupt is pending in isr4. isr3 3 rsc interrupt status register 3 pointer 0 b , no interrupt is pending in isr3. 1 b , at least one interrupt is pending in isr3. isr2 2 rsc interrupt status register 2 pointer 0 b , no interrupt is pending in isr2. 1 b , at least one interrupt is pending in isr2. isr1 1 rsc interrupt status register 1 pointer 0 b , no interrupt is pending in isr1. 1 b , at least one interrupt is pending in isr1. isr0 0 rsc interrupt status register 0 pointer always 0, because no isr0 exists. field bits type description uvf ,65 uvf ,65 uvf ,65 uvf ,65 uvf ,65 uvf ,65 uvf ,65 uvf ,65
data sheet 155 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionchannel interrupt status register channel interrupt status register this status register points to pending interrupts of channels 1to 8, see chapter 3.5.3 . cis offset reset value channel interrupt status register 006f h 00 h field bits type description gis8 7 rsc gis 8: global interrupt status of channel 8 0 b , no interrupt is pending on channel 8. 1 b , at least one interrupt is pending on channel 8, read gis of channel 8 for more information. gis7 6 rsc global interrupt status of channel 7 0 b , no interrupt is pending on channel 7. 1 b , at least one interrupt is pending on channel 7, read gis of channel 7 for more information. gis6 5 rsc global interrupt status of channel 6 0 b , no interrupt is pending on channel 6. 1 b , at least one interrupt is pending on channel 6, read gis of channel 6 for more information. gis5 4 rsc global interrupt status of channel 5 0 b , no interrupt is pending on channel 5. 1 b , at least one interrupt is pending on channel 5, read gis of channel 5 for more information. gis4 3 rsc global interrupt status of channel 4 0 b , no interrupt is pending on channel 4. 1 b , at least one interrupt is pending on channel 4, read gis of channel 4 for more information. gis3 2 rsc global interrupt status of channel 3 0 b , no interrupt is pending on channel 3. 1 b , at least one interrupt is pending on channel 3, read gis of channel 3 for more information. gis2 1 rsc global interrupt status of channel 2 0 b , no interrupt is pending on channel 2. 1 b , at least one interrupt is pending on channel 2, read gis of channel 2 for more information. gis1 0 rsc global interrupt status of channel 1 0 b , no interrupt is pending on channel 1. 1 b , at least one interrupt is pending on channel 1, read gis of channel 1 for more information. uvf *,6 uvf *,6 uvf *,6 uvf *,6 uvf *,6 uvf *,6 uvf *,6 uvf *,6
octalliu tm pef 22508 e register descriptionmulti function port input register data sheet 156 rev. 1.0, 2005-06-02 multi function port input register this register always reflects the state of the multi function ports, see chapter 3.12 . if used as an input, the according port should be switched to general purpose input mode. if not, the programmed output signal can be monitored through this register (see registers pc1 to pc3). mfpi offset reset value multi function port input register xxab h xx h field bits type description rpc 6 r rpc input level 0 b , low level on pin rpc. 1 b , high level on pin rpc. rpb 5 r rpb input level 0 b , low level on pin rpb. 1 b , high level on pin rpb. rpa 4 r rpa input level 0 b , low level on pin rpa. 1 b , high level on pin rpa. xpb 1 r xpb input level 0 b , low level on pin xpb. 1 b , high level on pin xpb. xpa 0 r xpa input level 0 b , low level on pin xpa. 1 b , high level on pin xpa. 5hv u 53& u 53% u 53$ 5hv u ;3% u ;3$
data sheet 157 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptioninterrupt status register 6 interrupt status register 6 global interrupt status 2 interrupt status register for the pll of the master clocking unit. isr6 offset reset value interrupt status register 6 xxac h 00 h field bits type description lilsu 1 rsc line in-band loop switching up interrupt see chapter 3.11.2 . 0 b , no line loop up code detected. 1 b , line loop up code detected and line loop is switched on if als.lils is set. lilsd 0 rsc line in-band loop switching down interrupt see chapter 3.11.2 . 0 b , no line loop down code detected. 1 b , line loop down code detected and line loop is switched off if als.lils is set. gis2 offset reset value global interrupt status 2 00ad h 00 h field bits type description pllls 1 r pll locked status information note: pllls is only a status bit, not an interrupt status bit, so type is r and not rsc. this bit is valid independent on value of comp. for comp = 0 this bit must be used instead of bit 7 of register cis which has then the function gis8. 0 b , pll is unlocked. 1 b , pll is locked 5hv uvf /,/68 uvf /,/6' 5hv u 3///6 uvf 3///&
octalliu tm pef 22508 e register descriptioninterrupt status register 7 data sheet 158 rev. 1.0, 2005-06-02 interrupt status register 7 all bits are reset when isr7 is read. if bit gcr.vis is set, interrupt statuses in isr7 are flagged although they are masked by register imr7. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis, see chapter 3.5.3 . plllc 0 rsc pll locked status change 0 b , no change of pll lock status since last read of this register. 1 b , pll lock status has changed since last read. status information is available in bit pllls. isr7 offset reset value interrupt status register 7 xxd8 h 00 h field bits type description xclkss1 4 rsc xclk source switched 1 see chapter 3.9.3 . shows if an automatically switching of the dco-x reference between tclk and fclkx was performed. if automatically switching is not enabled (cmr6.atcs = 0), this bit is always 0. note that the status of tclk is shown independent on cmr6.atc in clkstat .tclklos. 0 b , dco-x reference not switched. 1 b , dco-x reference has switched between tclk and fclkx. the xclk is always sourced by the dco-x output. xclkss0 3 rsc xclk source switched 0 see chapter 3.9.3 . shows if an automatically switching of the xclk source between tclk and dco-x output was performed. if automatically switching is not enabled (cmr6.atcs = 0), this bit is always 0. note that the status of tclk is shown independent on cmr6.atc in clkstat .tclklos. 0 b , xclk source not switched. 1 b , xclk source has switched automatically from tclk to dco-x output in case of tclk loss or automatically switched back from dco-x output to tclk in case that tclk is active again. the dco- x is always sourced by fclkx. field bits type description 5hv uvf ;&/.66 uvf ;&/.66 5hv
data sheet 159 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e register descriptionprbs status register prbs status register prbssta offset reset value prbs status register xxda h 0x h field bits type description prs 2:0 r prbs status information note: every change of the bits prs sets the interrupt bit isr1.llbsc if register bit lcr1.eprm is set. no pattern is also detected if signal ?alarm simulation? is active. detection of all_zero or all_ones is done over 12, 16, 21 or 24 consecutive bits, dependent on the choosed prbs polynomial (11, 15, 20 or 23). because every bit error in the prbs increments the bit error counter bec, no special status information like ?prbs detected with errors? is given here 000 b , no pattern detected. 001 b , reserved. 010 b , prbs pattern detected. 011 b , inverted prbs pattern detected. 100 b , reserved. 101 b , reserved. 110 b , all-zero pattern detected. 111 b , all-ones pattern detected. 5hv u 356
octalliu tm pef 22508 e register descriptionclock status register data sheet 160 rev. 1.0, 2005-06-02 clock status register the bits show the current status of the input clocks tclk and fclkx. clkstat offset reset value clock status register xxfe h xx h field bits type description tclklos 4 r loss of tclk status of tclk. note: see chapter 3.9.3 for more detail. 0 b , tclk is active. 1 b , tclk is lossed. fclkxlos 3 r loss of fclkx status of fclkx. note: see chapter 3.9.3 for more detail. 0 b , fclkx is active. 1 b , fclkx is lossed. 5hv u 7&/./26 u )&/.;/2 6 5hv
data sheet 161 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e package outlines 5 package outlines figure 39 shows the package outline. figure 39 pg-lbga-256-1 (plastic low profile ball grid array package), smd dimensions in mm note: the upper drawing shows the ?bottom view? of the package. ?0.1 ?0.25 0.3 min. 0.1 17 0.2 c 0.1 ?0.5 15 x 1 = 15 a16 index marking b m 256x ca c b 0.1 17 a 0.25 t1 1.5 max. c 1 index marking a1 1 m 15 x 1 = 15
octalliu tm pef 22508 e electrical characteristics data sheet 162 rev. 1.0, 2005-06-02 6 electrical characteristics in table 48 the absolute maximum ratings of the octalliutm are listed. attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 49 defines the maximum values of voltages and temperature which may be applied to guarantee proper operation of the octalliutm. table 48 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. ambient temperature under bias t a -40 ? 85 c ? storage temperature t stg -65 ? 125 c ? moisture level 3 temperature t ml3 ? ? 225 c according to ips j-std 020 ? ? 245 c according to infineon internal standard ic supply voltage (pads, digital) v dd -0.5 3.3 4.5 v ? ic supply voltage (core, digital) v ddc -0.5 1.8 2.4 v ? ic supply voltage receive (analog) v ddr -0.4 ? 4.5 v ? ic supply voltage transmit (analog) v ddx -0.4 ? 4.5 v ? receiver input signal with respect to ground v rlmax -0.8 ? 4.5 v rl1, rl2 voltage on any pin with respect to ground v max -0.4 ? 4.5 v except rl1, rl2 esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to jedec standard jesd22-a114. v esd,hbm ? ? 2000 v 2) 2) for rl1 and rl2 1500 v esd robustness 3) cdm 3) according to esd association standard ds5.3.1 - 1999 v esd,cdm ? ? 500 v ?
data sheet 163 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics note: in the operating range, the functions given in the circuit description are fulfilled. v dd , v ddr and v ddx have to be connected to the same voltage level, v ss , v ssr and v ssx have to be connected to ground level. table 49 operating range parameter symbol values unit note / test condition min. typ. max. ambient temperature t a -40 ? 85 c ? supply voltage digital pads v dd 3.13 3.30 3.46 v 3.3 v 5% 1) 1) voltage ripple on analog supply less than 50 mv supply voltage digital core v ddc 1.62 1.80 1.98 v 1.8 v 10% 1) supply voltage analog receiver v ddr 3.13 3.30 3.46 v 3.3 v 5% 1) supply voltage analog transmitter v ddx 3.13 3.30 3.46 v 3.3 v 5% 1) analog input voltages v rl 0 ? v ddr +0.3 v rl1, rl2 digital input voltages v id -0.4 ? 3.46 v v dd = 3.3 v 5 % ground v ss v ssr v ssx 0 ? 0 v ? table 50 dc characteristics parameter symbol values unit note / test condition min. typ. max. input low voltage v il -0.4 ? 0.8 v 1) input high voltage v ih 2.0 ? 3.46 v 1) output low voltage v ol v ss ? 0.45 v i ol = +2 ma 2) output high voltage v oh 2.4 ? v dd v i oh = -2 ma 2) average power supply current at 1.8 v supply (analog line interface mode) i dd18e1 ? ? 300 ma e1 application 3) lim1.drs = 0, prbs pattern; 2 mhz at framer interface i dd18t1 ? ? 250 ma t1 application 3) lim1.drs = 0, prbs pattern; 1.5 mhz at framer interface average power supply current at 3.3 v supply (analog line interface mode) i dd33e1 ? ? 370 ma e1 application 3) lim1.drs = 0, prbs pattern; 2 mhz at system interface i dd33t1 ? ? 370 ma t1 application 3) lim1.drs = 0, prbs pattern; 1.5 mhz at system interface average power supply current at 1.8 v supply (digital line interface mode) i dd18e1 ? ? 350 ma e1 application 3) lim1.drs = 1, prbs pattern; 16 mhz at system interface average power supply current at 3.3 v supply (digital line interface mode) i dd33t1 ? ? 25 ma e1 application 3) lim1.drs = 1, prbs pattern; 16 mhz at system interface input leakage current i il11 ? ? 1 a v in = v dd 4) ; all except rdo
octalliu tm pef 22508 e electrical characteristics data sheet 164 rev. 1.0, 2005-06-02 input leakage current i il12 ? ? 1 a v in = v ss 3) ; all except rdo input pullup current i ip 2 ? 15 a v in = v ss output leakage current i oz1 ? ? 1 a v out = tristate 1) v ss < v meas < v dd measured against v dd and v ss ; all except xl1/2 transmitter leakage current i tl ? ? 30 a xl1/2 = v ddx ; xpm2.xlt = 1 ? ? 30 a xl1/2 = v ssx ; xpm2.xlt = 1 transmitter output impedance r x ? ? 3 ? applies to xl1and xl2 5) transmitter output current i x ? ? 105 ma xl1, xl2 differential peak voltage of a mark (between xl1 and xl2) v x ? ? 2.15 v ? receiver peak voltage of a mark (at rl1 or rl2) v rl12 -0.45 ? 3.8 v rl1, rl2 -0.75 ? 4.1 v rz signals; must only be applied during t1 pulse over/undershoot according to ansi t1.403-1999 receiver differential peak voltage of a mark (between rl1 and rl2) v rl12 ? ? 4.0 v rl1, rl2 ? ? 4.63 v rz signals; must only be applied during t1 pulse over/undershoot according to ansi t1.403-1999 receiver input impedance z r ? 50 ? k ? 5) receiver sensitivity s rsh 0 ? 10 db rl1, rl2 lim0.eqon = 0 (short-haul) receiver sensitivity - s rlh -43 ? 0 db rl1, rl2 lim0.eqon = 1 (e1, long-haul) -36 ? 0 db rl1, rl2 lim0.eqon = 1 (t1/j1, long-haul) receiver input threshold v rth ? 45 ? % lim2.slt(1:0) = 11 b 5) ? 50 ? % lim2.slt(1:0) = 10 b 5) default setting ? 55 ? % lim2.slt(1:0) = 00 b 5) ? 67 ? % lim2.slt(1:0) = 01 b 5) multi purpose analog switch r dson 2.7 ? 7.1 ? ? r dsoff 100 ? ? k ? ? r dsondc ? ? 2 ma @ 125 o c r dson ? ? 25 ma @ 50% duty cycle table 50 dc characteristics (cont?d) parameter symbol values unit note / test condition min. typ. max.
data sheet 165 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics note: typical characteristics specify mean values expected over the production spread. if not specified otherwise, typical characteristics apply at t a = 25 c and 3.3 v supply voltage. loss-of-signal (los) detection limit v los 1560 ? 1710 mv ril(2:0) = 000 b 5) 790 ? 960 mv ril(2:0) = 001 b 5) 430 ? 500 mv ril(2:0) = 010 b 6) 220 ? 260 mv ril(2:0) = 011 b 5) 125 ? 130 mv ril(2:0) = 100 b 5) 65 ? 70 mv ril(2:0) = 101 b 5) 35 ? 40 mv ril(2:0) = 110 b 5) 10 ? 15 mv ril(2:0) = 111 b 5) 1) applies to all input pins except analog pins rlx 2) applies to all output pins except pins xlx 3) wiring conditions and external circuit configuration according to figure 58 and table 66 . 4) pin leakage is measured in a test mode with all internal pullups disabled. rdo pins are not tristatable, no leakage is measured. 5) parameter not tested in production 6) value measured in production to fulfil itu-t g.775 table 50 dc characteristics (cont?d) parameter symbol values unit note / test condition min. typ. max.
octalliu tm pef 22508 e electrical characteristics data sheet 166 rev. 1.0, 2005-06-02 6.1 ac characteristics 6.1.1 master clock timing figure 40 shows the timing and table 51 the appropriate timing parameter values of the master clock at the pin mclk. the accuracy is required to fulfill the jitter requirements, see chapter 3.7.9.1 and chapter 3.9.4 . figure 40 mclk timing table 51 mclk timing parameter values parameter symbol values unit note / test condition min. typ. max. clock period of mclk 1 ? 488 ? ns e1, fixed mode ? 648 ? ns t1/j1, fixed mode 50 ? 980.4 ns e1/t1/j1, flexible mode high phase of mclk 2 40 ? ? % ? low phase of mclk 3 40 ? ? % ? clock accuracy ? 32 1) 1) if clock divider programming fits without rounding ? 28 2) 2) if clock divider programming requires rounding ppm ? f0007 mclk 1 2 3
data sheet 167 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics 6.1.2 jtag boundary scan interface figure 41 shows the timing and table 52 the appropriate timing parameter values at the jtag pins to perform a boundary scan test of the octalliutm, see chapter 3.5.4 . figure 41 jtag boundary scan timing table 52 jtag boundary scan timing parameter values parameter symbol values unit note / test condition min. typ. max. trs reset active low time 1 200 ? ? ns ? tck period 2 250 ? ? ns ? tck high time 3 80 ? ? ns ? tck low time 4 80 ? ? ns ? tms, tdi setup time 5 40 ? ? ns ? tms, tdi hold time 6 40 ? ? ns ? tdati setup time 7 40 ? ? ns ? tdati hold time 8 40 ? ? ns ? tdo, tdato output delay 9 ? ? 100 ns ? f0120 tck tms, tdi tdati tdo, tdato trs 1 3 4 5 6 2 7 8 9
octalliu tm pef 22508 e electrical characteristics data sheet 168 rev. 1.0, 2005-06-02 6.1.3 reset figure 42 shows the timing and table 53 the appropriate timing parameter value at the pin res to perform a reset of the octalliutm. figure 42 reset timing 6.1.4 asynchronous microprocessor interface 6.1.4.1 intel bus interface mode figure 43 to figure 46 show the timing of the sci interface and table 54 the appropriate timing parameter values. figure 43 intel non-multiplexed address timing table 53 reset timing parameter value parameter symbol values unit note / test condition min. typ. max. res pulse width low 1 10 1) 1) while mclk is running ? ? s ? f0008 res 1 wr rd cs bhe ax 1 3 3a 2 itt10975
data sheet 169 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics figure 44 intel multiplexed address timing figure 45 intel read cycle timing wr rd 3 cs ale bhe ax 4 6 1 7 5 3a itt10977 7a o ct al_falc_f0121 cs rd wr dx 8 9 8 9 11 31 ready 32 33 30
octalliu tm pef 22508 e electrical characteristics data sheet 170 rev. 1.0, 2005-06-02 figure 46 intel write cycle timing table 54 intel bus interface timing parameter values parameter symbol values unit note / test condition min. typ. max. address, bhe setup time 1 5 ? ? ns ? address, bhe hold time 2 0 ? ? ns ? cs setup time 3 0 ? ? ns ? cs hold time 3a 0 ? ? ns ? address, bhe stable before ale inactive 4 10 ? ? ns ? address, bhe hold after ale inactive 5 10 ? ? ns ? ale pulse width 6 30 ? ? ns ? ale setup time before rd or wr 7 0 ? ? ns ? ale hold time after rd or wr 7a 30 ? ? ns ? rd , wr pulse width 8 80 ? ? ns ? rd, wr control interval 9 70 ? ? ns ? data hold after rd inactive 11 10 ? 30 ns ? data stable before wr inactive 15 30 ? ? ns ? data hold after wr inactive 16 10 ? ? ns ? rd or wr delay after ready 30 ? ? 40 ns ? ready hold time after rd or wr 31 5 ? ? ns ? data stable before ready 32 ? ? 90 ns ? rd to ready delay 33 ? ? 90 ns ? wr to ready delay 34 ? ? 90 ns ? o ctal_falc_intel_write_cycle cs rd wr dx 8 9 8 9 15 16 30 ready 34 31
data sheet 171 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics 6.1.4.2 motorola bus interface mode figure 47 and figure 48 show the timing of the sci interface and table 55 the appropriate timing parameter values. figure 47 motorola read cycle timing figure 48 motorola write cycle timing o ct alfalc_f0122 cs ax, ble 17 ds rw dx 18 22 19 19a 20 21 23 25 41 40 dtack 43 44 24 o ct alfalc_mot _wr it e_cycle cs ax, ble 17 ds rw dx 18 22a 19 19a 20 21 23 27 26 40 dtack 42 41
octalliu tm pef 22508 e electrical characteristics data sheet 172 rev. 1.0, 2005-06-02 6.1.4.3 sci interface figure 49 shows the timing of the sci interface and table 56 the appropriate timing parameter values. figure 49 sci interface timing table 55 motorola bus interface timing parameter values parameter symbol values unit note / test condition min. typ. max. address, ble setup time before ds active 17 15 ? ? ns ? address, ble hold after ds inactive 18 0 ? ? ns ? cs active before ds active 19 0 ? ? ns ? cs hold after ds inactive 19a 0 ? ? ns ? r w stable before ds active 20 10 ? ? ns ? r w hold after ds inactive 21 0 ? ? ns ? ds pulse width (read access) 22 80 ? ? ns ? ds pulse width (write access) 22a 80 ? ? ns ? ds control interval 23 70 ? ? ns ? data valid after ds active (read access) 24 ? ? 75 ns ? data hold after ds inactive (read access) 25 ? ? 30 ns ? data stable before ds active (write access) 26 30 ? ? ns ? data hold after ds inactive (write access) 27 10 ? ? ns ? ds delay after dtack 40 ? ? 25 ns ? dtack hold time after ds inactive 41 10 ? ? ns ? ds to dtack delay for write 42 ? ? 100 ns ? ds to dtack delay for read 43 ? ? 100 ns ? data strobe before dtack 44 0 ? ? ns ? sci_clk oct alli u_sci _t iming 1 2 3 4 5 6 sci_txd sci_rxd
data sheet 173 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics 6.1.4.4 spi interface figure 50 shows the timing of the sci interface and table 57 the appropriate timing parameter values. figure 50 spi interface timing table 56 sci timing parameter values parameter symbol values unit note / test condition min. typ. max. sci_clk cycle time in full duplex mode 1 170 ? ? ns ? sci_clk cycle time in half duplex mode 1 500 ? ? ns ? sci_clk clock low time 2 76.5 ? ? ns ? sci_clk clock high time 3 76.5 ? ? ns ? sci_rxd setup time before sci_clk 4 0 ? ? ns ? sci_rxd hold time after sci_clk 5 0 ? ? ns ? sci_txd delay time after sci_clk 6 ? ? 30 ns ? table 57 spi timing parameter values parameter symbol values unit note / test condition min. typ. max. sclk frequency ? ? ? 100 mhz ? cs setup time before sclk 1 40 ? ? ns ? cs hold time after sclk 2 40 ? ? ns ? sdi hold time after sclk 3 40 ? ? ns ? sdi setup time before sclk 4 40 ? ? ns ? sclk low time 5 45 ? ? ns ? sclk high time 6 45 ? ? ns ? cs high time 7 100 ? ? ns ? clock disable time before sclk 8 50 ? ? ns ? sdo output stable after sclk 9 ? ? 40 ns ? sdo output hold after cs disable 10 ? ? 40 ns ? sdo output high impedance after sclk 11 0 ? ? ns ? o ct al_falc_spi _t iming cs sclk sdi hi gh impedance sdo 1 43 6 5 7 8 2 9 11 10
octalliu tm pef 22508 e electrical characteristics data sheet 174 rev. 1.0, 2005-06-02 6.1.5 digital interface (framer interface) figure 51 , figure 52 , figure 53 and figure 54 show the timing and table 59 , table 60 , table 61 the appropriate timing parameter values at the digital interface of the octalliutm. figure 51 fclkx output timing figure 52 fclkr output timing table 58 fclkx timing parameter values parameter symbol values unit note / test condition min. typ. max. fclkx clock period e1 1 ? 488 ? ns ? fclkx clock period t1/j1 1 ? 648 ? ns ? fclkx high 2 40 ? ? % ? fclkx low 3 40 ? ? % ? xdi, xdin setup time 4 5 ? ? ns ? xdi, xdin hold time 5 15 ? ? ns ? fclkx (tpe=0) fclkx (tpe=1) xdi, xdin 4 5 2 3 1 data change edge oct alli u_f 0055 octalliu _f005 4 fclkr (rpe=1) fclkr (rpe=0) rdo, rdon 4 2 3 1 data change edge
data sheet 175 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics figure 53 sync timing figure 54 fsc timing table 59 fclkr timing parameter values parameter symbol values unit note / test condition min. typ. max. fclkr clock period e1 1 ? 488 ? ns ? fclkr clock period t1/j1 1 ? 648 ? ns ? fclkr high 2 40 ? ? % ? fclkr low 3 40 ? ? % ? rdo, rdon delay 4 0 ? 35 ns ? table 60 sync timing parameter values parameter symbol values unit note / test condition min. typ. max. sync high time 1 125 ? ? ns ? sync low time 2 122 ? ? ns ? table 61 fsc timing parameter values parameter symbol values unit note / test condition min. typ. max. fsc period 1 ? 125 ? s ? fsc low time e1 2 ? 244 ? ns ? fsc low time t1/j1 2 ? 324 ? ns ? rclk to fsc delay 3 ? 50 80 ns ? f005 6 sync 1 2 f0053 fsc 2 1 rclk 3
octalliu tm pef 22508 e electrical characteristics data sheet 176 rev. 1.0, 2005-06-02 6.1.6 pulse templates - transmitter the transmitter includes a programmable pulse shaper to generate transmit pulse masks according to: ? for t1: fcc68; ansi t1. 403 1999, figure 4; itu-t g703 11/2001, figure 10 (for different cable lengths), see figure 56 . for measurement configuration were r load = 100 ? see figure 33 . ? for e1: itu-t g703 11/2001, figure 15 (for 0 m cable length), see figure 55 ; itu-t g703 11/2001, figure 20 (for dcim mode). for measurement configuration were r load = 120 ? or r load = 75 ? see figure 32 . the transmit pulse form is programmed either ? by the registers xmp(2:0) compatible to the quadliu?, see table 24 and table 25 , if the register bit xpm2.xpdis is cleared ? or by the registers txp(16:1), if the register bit xpm2.xpdis is set, see table 26 and table 27 . 6.1.6.1 pulse template e1 with the given values in table 25 or table 27 , for transformer ratio: 1 : 2.4, cable type awg24 and with r load = 120 ? the pulse mask according to itu-t g703 11/2001, see figure 55 , is fulfilled. figure 55 e1 pulse shape at transmitter output 6.1.6.2 pulse template t1 with the given values in table 24 or table 26 , for transformer ratio: 1 : 2.4, cable type awg24 and with r load = 100 ? the pulse mask according to itu-t g703 11/2001, figure 10, see figure 56 , is fulfilled. itd00573 10 % 10 % % 10 10 % % 10 10 % 20 % 269 ns (244 + 25) (244 - 50) ns 194 219 ns (244 - 25) ns 244 (244 + 244) ns 488 % 0 50 % % v =100 nominal pulse % 20 20 %
data sheet 177 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics figure 56 t1 pulse shape at the cross connect point 6.2 capacitances values of capacitances of the input and of the output pins of the octalliutm are listed in table 63 . table 62 t1 pulse template at cross connect point (t1.102 1) ) 1) requirements of itu-t g.703 are also fulfilled maximum curve minimum curve time [ns] level [%] 2) 2) 100 % value must be in the range of 2.4 v and 3.6 v; tested at 0 and 200 m using pic 22awg cable characteristics. time [ns] level [%] 0 5 0 -5 250 5 350 -5 325 80 350 50 325 115 400 95 425 115 500 95 500 105 600 90 675 105 650 50 725 -7 650 -45 1100 5 800 -45 1250 5 925 -20 1100 -5 1250 -5 table 63 capacitances parameter symbol values unit note / test condition min. typ. max. input capacitance 1) 1) not tested in production c in 5 ? 10 pf ? output capacitance 1) c out 8 ? 15 pf all except xlx output capacitance 1) c out 8 ? 20 pf xlx itd00574 % 100 = v 50 % 0 -50 % 0 250 500 750 1000 ns t normalized amplitude
octalliu tm pef 22508 e electrical characteristics data sheet 178 rev. 1.0, 2005-06-02 6.3 package characteristics the following table shows the thermal characteristics of the bga package together with different pcbs. 6.4 test configuration 6.4.1 ac tests the values for ac characteristics of the chapters above are based on the following definitions of levels and load capacitances: figure 57 input/output waveforms for ac testing table 64 package characteristic values parameter symbol values unit note / test condition min. typ. max. thermal resistance between junction and pcb for bga 256 package 1) r thjab ? 29 ? k/w single layer pcb, natural convection ? 23.7 ? k/w 4 layer pcb, natural convection ? 22.4 ? k/w 6 layer pcb, natural convection ? 22.3 ? k/w 10 layer pcb, natural convection junction temperature r j ? 125 c ? table 65 ac test conditions parameter symbol values unit note / test condition load capacitance c l 50 pf ? input voltage high v ih 2.4 v all except rlx input voltage low v il 0.4 v all except rlx test voltage high v th 2.0 v all except xlx test voltage low v tl 0.8 v all except xlx f0067 tim ing test points v th v tl device under test c l test levels v ih v il drive levels
data sheet 179 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e electrical characteristics 6.4.2 power supply test for power supply test all eight channels of the octalliutm are active. transmitter and receiver are configured as for typical applications. the transmitted data are looped back to the receiver by a short line as shown in figure 58 . on the system side the interfaces of all channels work independent from another (no multiplex mode is configured). figure 58 device configuration for power supply testing table 66 power supply test conditions e1 parameter symbol values unit note / test condition load resistance at transmitter r 1 7.5 ? 1%; xl3 and xl4 are left open; pc6.tsre = 1 termination resistance at receiver r 2 120 ? 1%; integrated receive line resistor r term is switched off (lim0.rtrs =0) line impedance r l 120 ? ? line length l < 0.2 m ? transformer ratio transmit tt1 : tt2 2.4 : 1 ? transformer ratio receive tr1 : tr2 1 : 1 ? framer interface frequency xclk rclk 2.048 mhz ? test signalactive channels (dcos active, 2-frame buffer)4 ? 2 15 -1 ? prbs pattern pulse mask programming (compatible to quadliu?) xpm2 40 h ? pulse mask according to itu-t g703 11/2001, see figure 55 xpm1 03 h ? xpm0 7b h ? ambient temperature ? 85 c ? octalliu tm r 1 r 2 v dd x v ddr v dd t t1 : t t2 t r1 : t r2 z 0 r 1 l oct alli u_f 0176 v ddc digital interfac e 8 x
octalliu tm pef 22508 e electrical characteristics data sheet 180 rev. 1.0, 2005-06-02 table 67 power supply test conditions t1/j1 parameter symbol values unit note / test condition load resistance r 1 2 ? 1%; xl3 and xl4 are left open; pc6.tsre = 1 termination resistance r 2 100 ? 1%; integrated receive line resistor r term is switched off (lim0.rtrs =0) line impedance r l 100 ? ? line length l < 0.2 m ? transformer ratio transmit tt1 : tt2 2.4 : 1 ? ? transformer ratio receive tr1 : tr2 1 : 1 ? ? framer interface frequency xclk rclk 1.544 mhz ? test signalactive channels (dcos active, 2-frame buffer)4 ? 2 15 -1 ? prbs pattern pulse mask programming (compatible to quadliu?) xpm2 02 h ? pulse mask according to itu-t g703 11/2001, figure 10, see figure 56 xpm1 27 h ? xpm0 9f h ? ambient temperature ? 85 c ?
data sheet 181 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e operational description 7 operational description 7.1 operational overview every of the eight channels of the octalliu tm can be operated in two clock modes, which are either e1 mode or t1/j1 mode, selected by the register bit gcm2.vfreq_en, see chapter 3.5.5 : in the so called ?flexible master clocking mode? (gcm2.vfreq_en = 1) all eight ports can work in e1 or in t1 mode individually, independent from another. in the so called ?clocking fixed mode? (gcm2.vfreq_en = 0) all eight ports must work together either in e1 or in t1 mode. the device is programmable via one of the three integrated micro controller interfaces which are selected by strapping of the pins im(1:0): the asynchronous interface has two modes: intel (im(1:0) = 00 b ) and motorola (im(1:0) = 01 b ). this interface enables byte or word access to all control and status registers, see chapter 3.5.1 . spi interface (im(1:0) = 10 b ), see chapter 3.5.2.2 . sci interface (im(1:0) = 11 b ), see chapter 3.5.2.1 . the octalliu tm has three different kinds of registers: the control registers configure the whole device and have write and read access. the status registers are read-only and are updated continuously. normally, the processor reads the status registers periodically to analyze the alarm status and signaling data. the interrupt status registers are read-only and are cleared by reading (?rsc?). they are updated (set) continuously. normally, the processor reads the interrupt status registers after an interrupt occurs at pin int. masking can be done with the appropriate interrupt mask registers. mask registers are control registers. all this registers can be separate into two groups: global registers are not belonging especially to one of the eight channels. the higher address byte is 00 h . the other registers are belonging to one of the eight channels. the higher address bytes - marked as xx h in the register description - are identical to the numbers 0 up to 7 of the appropriate channels. so every of this registers exist eight time in the whole device. 7.2 device reset after the device is powered up, the octalliu tm must be forced to the reset state first. the octalliu tm is forced to the reset state if a low signal is input on pin res for a minimum period of 10 s, see figure 42 . during reset the octalliu tm needs an active clock on pin mclk the pin comp must be 0. the pins im(1:0) must have defined values to select the micro controller interface. only if im(1:0) = 11 b (sci interface is selected) the pins a(5:0) must have defined values to select the sci source address of the device. only if im1 = 1 (sci or spi interface is selected) the pins d(15:5) must have defined values to configure the central pll in the master clocking unit of the device. during and after reset all internal flip-flops are reset and most of the control registers are initialized with default values. signals (for example rl1/2 receive line) should not be applied before the device is powered up. after reset the complete device is initialized, especially to e1 operation and ?flexible master clocking mode?. the complete initialization is listed in table 68 . additionally all interrupt mask registers imr1, imr3, imr4, imr6 and imr7 are initialized to ff h , so that not masking is performed. after reset the octalliu tm must be configured first. general guidelines for configuration are described in chapter 7.4 for e1 mode and chapter 7.5 for t1/j1 mode. for reset see also chapter 3.5.5.1 .
octalliu tm pef 22508 e operational description data sheet 182 rev. 1.0, 2005-06-02 7.3 device initialization after reset, the octalliu tm is initialized for e1 with register values listed in the following table. 7.4 device configuration in e1 mode e1 configuration for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and etsi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 69 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, can be programmed simultaneously. the bit mr1.pmod should always be kept low (otherwise t1/j1 mode is selected). table 68 initial values after reset register reset value meaning lim0, lim1, pcd, pcr 00 h , 00 h , 00 h , 00 h slave mode, local loop off analog interface selected; remote loop off; pulse count for los detection cleared; pulse count for los recovery cleared xpm(2:0) 40 h , 03 h , 7b h e1 transmit pulse template for 0 m but with unreduced amplitude (note that transmitter is in tristate mode) imr(7:0) ff h all interrupts are disabled gcr 00 h internal second timer, power on cmr1 00 h rclk output: dpll clock, dco-x enabled, dco-x internal reference clock cmr2 00 h rclk selected, xclk selected pc(3:1) 00 h , f0 h 00 h , 00 h functions of ports rp(a to b) are reserved, function of port rpc is rclk output (but is only pulled up, because pc5.crp = 0 after reset), functions of ports xp(a to b) are reserved. pc5 00 h fclkr, fclkx, rclk configured to inputs, gcm(6:1) gcm2 = 10 h , others 00 h ?flexible master clocking mode? selected gpc(5:3) 65 h , 43 h , 21 h source for rclk1 up to rclk7 are the appropriate channels (only valid for comp = 0) gpc6 07 h quadliu compatible system interface multiplexed modes are selected, source for rclk8 is channel 8 (both only valid for comp = 0) cmr(6:4) 00 h recovered line clock drives rclk gpc2 00 h source for sec and rclk1 is channel 1 txp(16:1) txp(1:8) = 38 h txp(9:16) = 00 h this registers are not used after reset because xpm2.xpdis = 0 inbldtr 00 h minimum in-band loop detection time als 00 h no automatic loop switching is performed prbsts(4:1) all 00 h no time slots are selected for prbs pattern
data sheet 183 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e operational description features like alarm simulation etc. are activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to ?00? hex. all control registers (except xs(16:1), cmdr, dec) are of type read/write. specific e1 register settings the following is a suggestion for a basic configuration to meet most of the e1 requirements. depending on different applications and requirement any other configuration can be used. attention: after the device configuration a softwa re reset should be executed by setting of bits cmdr.xres/rres. 7.5 device configuration in t1/j1 mode after reset, the octalliu tm is initialized for e1 doubleframe format. to configure t1/j1 mode, bit mr1.pmod has to be set high. after the internal clocking is settled to t1/j1mode (takes up to 20 s), the following register values are initialized: t1/j1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after res goes inactive (high). both the basic and the operational parameters table 69 configuration parameters (e1) basic set up master clocking mode gcm(6:1) according to external mclk clock frequency e1 mode select mr1.pmod = 0 clock system configuration cmr(3:1), gpc1; if comp = 0 cmr(6:4) and gpc(6:2) specification of line interface lim0, lim1, xpm(2:0) specification of transmit pulse mask xpm(2:0) or txp(16:1) line interface coding mr0.xc(1:0), mr0.rc(1:0) loss-of-signal detection/recovery conditions pcd, pcr, lim1, lim2 multi function port selection pc(3:1) table 70 line interface configuration (e1) mr2.dais = 1 disables ais insertion into the data stream (necessary for proper operation) mr2.rtm = 1 sets the receive dual elastic store in a ?free running? mode (necessary for proper operation) mr5.tt0 = 1 enables transmit transparent mode (necessary for proper operation) mr5.xtm = 1 sets the transmitter in a ?free running? mode (necessary for proper operation) mr0.xc0/ mr0.rc0/ lim1.drs mr3.cmi the octalliu tm supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami and hdb3 are supported. for the digital line interface modes (dual- or single-rail) the octalliu tm supports ami, hdb3, cmi (with and without hdb3 precoding). pcd = 0a h los detection after 176 consecutive ?zeros? (fulfills g.775). pcr = 15 h los recovery after 22 ?ones? in the pcd interval. (fulfills g.775). lim1.ril(2:0) = 02 h los threshold of 0.6 v (fulfills g.775).
octalliu tm pef 22508 e operational description data sheet 184 rev. 1.0, 2005-06-02 must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 71 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, can be programmed simultaneously. the bit mr1.pmod must always be kept high (otherwise e1 mode is selected). j1 mode is selected by additionally setting rc0.sjr = 1. features like channel loop-back, idle channel activation, clear channel activation, extensions for signaling support, alarm simulation, etc. are activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 h . all control registers (except xs(12:1), cmdr, dec) are of type read/write specific t1/j1 configuration the following is a suggestion for a basic configuration to meet most of the t1/j1 requirements. depending on different applications and requirements any other configuration can be used. table 71 configuration parameters (t1/j1) basic set up t1 j1 master clocking mode gcm(6:1) according to external mclk clock frequency t1/j1 mode select mr1.pmod = 1, mr1.pmod = 1, clock system configuration cmr(3:1), gpc1; if comp = 0 cmr(6:4) and gpc(6:2) specification of line interface lim0, lim1, specification of transmit pulse mask xpm(2:0) or txp(16:1) line interface coding mr0.xc(1:0), mr0.rc(1:0) loss-of-signal detection/recovery conditions pcd, pcr, lim1, lim2 ais to framer interface mr2.xais multi function port selection pc(3:1) table 72 line interface configuration (t1/j1) register function mr2.dais = 1 disables ais insertion into the data stream (necessary for proper operation) loop.rtm = 1 sets the receive dual elastic store in a ?free running? mode (necessary for proper operation) mr4.tm = 1 enables transparent mode (necessary for proper operation) mr5.xtm = 1 sets the transmitter in a ?free running? mode (necessary for proper operation) ccb(3:1) = ff h ? ?clear channel? mode is selected (necessary for proper operation only if ami code is selected) mr0.xc0/1 mr0.rc0/1 lim1.drs ccb(3:1) dic3.cmi the octalliu tm supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami (with and without bit 7stuffing) and b8zs are supported. for the digital line interface modes (dual- or single-rail) the octalliu tm supports ami (with and without bit 7 stuffing), b8zs (with and without b8zs precoding). pcd = 0a h los detection after 176 consecutive ?zeros? (fulfills g.775/telcordia (bellcore)/at&t)
data sheet 185 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e operational description note: after the device configuration a software reset should be executed by setting of bits cmdr.xres/rres. pcr = 15 h los recovery after 22 ?ones? in the pcd interval (fulfills g.775, bellcore/at&t). lim1.ril(2:0) = 02 h los threshold of 0.6 v (fulfills g.775). gcr.sci = 1 additional recovery interrupts. help to meet alarm activation and deactivation conditions in time. lim2.los1 = 1 automatic pulse-density check on 15 consecutive zeros for los recovery condition (bellcore requirement) table 72 line interface configuration (t1/j1) register function
octalliu tm pef 22508 e operational description data sheet 186 rev. 1.0, 2005-06-02 7.6 device configuration for digi tal clock interface mode (dcim) the following table shows the necessary configuration for the digital clock interface mode (dcim), see itu-t g.703 11/2001, chapter 13. the receive clock at rl1/rl2 (2.048 mhz) is supported at multi function port rpc. the transmit clock at fclkx (2.048 mhz) is transmitted at xl1/xl2. dcim mode is standardized only for 2.048 mhz (e1 mode, mr1.pmod = 0). the octalliu tm can handle also 1.544 mhz if mr1.pmod = 1. table 73 device configuration for dcim mode mr1.pmod selects 2.048 mhz or 1.544 mhz, see text above lim0.dcim = 1 selects dcim mode. lim1.rl = 0 tx clock mode. cmr1.dxss = 0 cmr1.dxja = 0 lim1.drs = 0 mr0.rc(1:0) = 10 b line interface mode rx mr0.xc(1:0) = 10 b line interface mode tx pc1.rpc1(3:0) = 1111 b select rclk as output pc5.crp = 1 cmr1.drss(1:0) or cmr5.drss(2:0) : select the appropriate channel rx clock mode cmr1.dcs = 1 lim0.mas = 0 cmr1.rs(1:0) = 10 b or cmr4.rs(2:0) = 010 b gcm(1:8) see chapter 3.5.5 and gcm6 configure clock system lim2.scf, cmr6.scfx, cmr2.ecfax, cmr2.ecfar, cmr3:cfax(3:0), cmr3.cfar(3:0), cmr4.iar(4:0), cmr5.iax(4:0): see chapter 3.7.9 and table 18 configure dco-x and dco-r dic1.rbs(1:0) = 10 b configure elastic buffers dic1.xbs(1:0) = 11 b
data sheet 187 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e appendix 8 appendix 8.1 protection circuitry the design in figure 59 shows an example of how to build up a generic e1/t1/j1 platform. the circuit shown has been successfully checked against itu-t k.20 and k.21 lightning surge tests (basic level). figure 59 protection circuitry examples (shown for one channel) 8.2 application notes several application notes and technical documentation provide additional information. online access to supporting information is available on the internet page: http://www.infineon.com/octalliu on the same page you find as well the boundary scan file for octalliu tm version 1.1 (bsdl file) 8.3 software support the following software package is provided together with the octalliu tm reference system easy 2256: e1 and t1 driver functions supporting different etsi, at&t and telcordia (former: bellcore) requirements ibis model for octalliu tm version 1.1 (according to ansi/eia-656) ?flexible master clock calculator?, which calculates the required settings for the registers gcm(1:8) depending on the external master clock frequency (mclk) ?external line front end calculator?, which provides an easy method to optimize the external components depending on the selected application type.r the both calculators run under a win9x/nt environment. calculation results are traced an can be stored in a file or printed out for documentation. screen shots of both programs are shown in figure 60 and figure 61 below. octalliu_f0262_2 fuse 1.25 a r2 r3 r3 rj45 octalliu tm rl1 rl2 xl1 xl2 r1 r1 1:1 1:2.4 v dd v ss v dd v ss fuse 1.25 a fuse 1.25 a fuse 1.25 a a a b a a b a smp 100lc-35 (~65 pf) b smp p3500sc (~60 pf) ptc ptc ptc ptc xl3 xl4
octalliu tm pef 22508 e appendix data sheet 188 rev. 1.0, 2005-06-02 figure 60 screen shot of the ?master clock frequency calculator? f0126
data sheet 189 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e appendix figure 61 screen shot of the ?external line frontend calculator? f0198_2256
octalliu tm pef 22508 e data sheet 190 rev. 1.0, 2005-06-02 terminology a a/d analog to digital adc analog to digital converter ais alarm indication signal (blue alarm) agc automatic gain control alos analog loss of signal ami alternate mark inversion ansi american national standards institute atm asynchronous transfer mode auxp auxiliary pattern b b8zs binary 8 zero supression (line coding to avoid too long strings of consecutive "0") bellcore bell communications research bpv bipolar violation bsn backward sequence number c cdr clock and data recovery cis channel interrupt status cmi coded mark inversion code (also known as 1t2b code) d d/a digital to analog dac digital to analog converter dcim digital clock interface mode dco digitally controlled oscillator dco-r dco of receiver dco-x dco of transmitter dl digital loop dpll digitally controlled phase locked loop ds1 digital signal level 1 e esd electrostatic discharge easy evaluation system for falc and liu products eq equalizer etsi european telecommunication standards institute f falc? framing and line interface component fcc us federal communication commission fcs frame check sequence (used in ppr) g
data sheet 191 rev. 1.0, 2005-06-02 octalliu tm pef 22508 e gis global interrupt status h hbm human body model for esd classification hdb3 high density bipolar of order 3 i ibis i/o buffer information specification (ansi/eia-656) ibl in band loop isdn integrated services digital network itu international telecommunications group j jatt jitter attenuator jtag joined test action group l lbo line build out lcv line code violation liu line interface unit ll local loop llb line loop back los loss of signal (red alarm) lsb least significant bit m mfp multi function port msb most significant bit mux multiplexer n nrz non return to zero signal p pcm pulse code modulation pd pull down resistor pdv pulse density violation plb payload loop back pll phase locked loop pmqfp plastic metric quad flat pack (device package) prbs pseudo random binary sequence ptqfp plastic thin metric quad flat pack (device package) pu pull up resistor r rai remote alarm indication (yellow alarm) ram random access memory rdi remote defect indication rl remote loop rlm receive line monitoring rom read-only memory
octalliu tm pef 22508 e data sheet 192 rev. 1.0, 2005-06-02 rx receiver s sapi service access point identifier (special octet in ppr) sci serial controlinterface spi serial peripheral interface sidactor overvoltage protection device for transmission lines t tap test access port tei terminal endpoint identifier (special octet in ppr) tx transmitter u ui unit interval z zcs zero code suppression
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